Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h

   1 /**
   2
   3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchRegsRcrb.h
  11
  12   @brief
  13   Register names for VLV Chipset Configuration Registers
  14
  15   Conventions:
  16
  17   - Prefixes:
  18     Definitions beginning with "R_" are registers
  19     Definitions beginning with "B_" are bits within registers
  20     Definitions beginning with "V_" are meaningful values of bits within the registers
  21     Definitions beginning with "S_" are register sizes
  22     Definitions beginning with "N_" are the bit position
  23   - In general, PCH registers are denoted by "_PCH_" in register names
  24   - Registers / bits that are different between PCH generations are denoted by
  25     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  26   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  27     at the end of the register/bit names
  28   - Registers / bits of new devices introduced in a PCH generation will be just named
  29     as "_PCH_" without <generation_name> inserted.
  30
  31 **/
  32 #ifndef _PCH_REGS_RCRB_H_
  33 #define _PCH_REGS_RCRB_H_
  34
  35 ///
  36 /// Chipset Configuration Registers (Memory space)
  37 /// RCBA
  38 ///
  39 #define R_PCH_RCRB_GCS                    0x00  // General Control and Status
  40 #define B_PCH_RCRB_GCS_BBSIZE             (BIT30 | BIT29) // Boot Block Size
  41 #define B_PCH_RCRB_GCS_BBS                (BIT11 | BIT10) // Boot BIOS Straps
  42 #define V_PCH_RCRB_GCS_BBS_SPI            (3 << 10) // Boot BIOS strapped to SPI
  43 #define V_PCH_RCRB_GCS_BBS_LPC            (0 << 10) // Boot BIOS strapped to LPC
  44 #define B_PCH_RCRB_GCS_TS                 BIT1 // Top Swap
  45 #define B_PCH_RCRB_GCS_BILD               BIT0 // BIOS Interface Lock-Down
  46
  47
  48 #endif