Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h

   1 /**
   2
   3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchRegsSata.h
  11
  12   @brief
  13   Register names for VLV SATA controllers
  14
  15   Conventions:
  16
  17   - Prefixes:
  18     Definitions beginning with "R_" are registers
  19     Definitions beginning with "B_" are bits within registers
  20     Definitions beginning with "V_" are meaningful values of bits within the registers
  21     Definitions beginning with "S_" are register sizes
  22     Definitions beginning with "N_" are the bit position
  23   - In general, PCH registers are denoted by "_PCH_" in register names
  24   - Registers / bits that are different between PCH generations are denoted by
  25     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  26   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  27     at the end of the register/bit names
  28   - Registers / bits of new devices introduced in a PCH generation will be just named
  29     as "_PCH_" without <generation_name> inserted.
  30
  31 **/
  32 #ifndef _PCH_REGS_SATA_H_
  33 #define _PCH_REGS_SATA_H_
  34
  35 ///
  36 /// VLV SATA Message Bus
  37 ///
  38 #define PCH_SATA_PHY_PORT_ID                0xA3  // SATA PHY Port ID
  39 #define PCH_SATA_PHY_MMIO_READ_OPCODE       0x00  // CUnit to SATA PHY MMIO Read Opcode
  40 #define PCH_SATA_PHY_MMIO_WRITE_OPCODE      0x01  // CUnit to SATA PHY MMIO Write Opcode
  41
  42 ///
  43 ///  SATA Controller Registers (D19:F0)
  44 ///
  45 #define PCI_DEVICE_NUMBER_PCH_SATA          19
  46 #define PCI_FUNCTION_NUMBER_PCH_SATA        0
  47
  48 #define R_PCH_SATA_ID                       0x00  // Identifiers
  49 #define B_PCH_SATA_ID_DID                   0xFFFF0000 // Device ID
  50 #define B_PCH_SATA_ID_VID                   0x0000FFFF // Vendor ID
  51 #define V_PCH_SATA_VENDOR_ID                V_PCH_INTEL_VENDOR_ID
  52 #define V_PCH_SATA_DEVICE_ID_D_IDE          0x0F20  // Desktop IDE Mode (Ports 0 and 1)
  53 #define V_PCH_SATA_DEVICE_ID_D_AHCI         0x0F22  // Desktop AHCI Mode (Ports 0 and 1)
  54 #define V_PCH_SATA_DEVICE_ID_D_RAID         0x2822  // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
  55
  56 #define V_PCH_SATA_DEVICE_ID_M_IDE          0x0F21  // Mobile IDE Mode (Ports 0 and 1)
  57 #define V_PCH_SATA_DEVICE_ID_M_AHCI         0x0F23  // Mobile AHCI Mode (Ports 0 and 1)
  58 #define V_PCH_SATA_DEVICE_ID_M_RAID         0x282A  // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
  59
  60 #define R_PCH_SATA_COMMAND                  0x04  // Command
  61 #define B_PCH_SATA_COMMAND_INT_DIS          BIT10 // Interrupt Disable
  62 #define B_PCH_SATA_COMMAND_FBE              BIT9  // Fast Back-to-back Enable
  63 #define B_PCH_SATA_COMMAND_SERR_EN          BIT8  // SERR# Enable
  64 #define B_PCH_SATA_COMMAND_WCC              BIT7  // Wait Cycle Enable
  65 #define B_PCH_SATA_COMMAND_PER              BIT6  // Parity Error Response Enable
  66 #define B_PCH_SATA_COMMAND_VPS              BIT5  // VGA Palette Snooping Enable
  67 #define B_PCH_SATA_COMMAND_PMWE             BIT4  // Memory Write and Invalidate Enable
  68 #define B_PCH_SATA_COMMAND_SCE              BIT3  // Special Cycle Enable
  69 #define B_PCH_SATA_COMMAND_BME              BIT2  // Bus Master Enable
  70 #define B_PCH_SATA_COMMAND_MSE              BIT1  // Memory Space Enable
  71 #define B_PCH_SATA_COMMAND_IOSE             BIT0  // I/O Space Enable
  72
  73 #define R_PCH_SATA_PCISTS                   0x06  // Device Status
  74 #define B_PCH_SATA_PCISTS_DPE               BIT15 // Detected Parity Error
  75 #define B_PCH_SATA_PCISTS_SSE               BIT14 // Signaled System Error
  76 #define B_PCH_SATA_PCISTS_RMA               BIT13 // Received Master-Abort Status
  77 #define B_PCH_SATA_PCISTS_RTA               BIT12 // Received Target-Abort Status
  78 #define B_PCH_SATA_PCISTS_STA               BIT11 // Signaled Target-Abort Status
  79 #define B_PCH_SATA_PCISTS_DEV_STS_MASK      (BIT10 | BIT9) // DEVSEL# Timing Status
  80 #define B_PCH_SATA_PCISTS_DPED              BIT8  // Master Data Parity Error Detected
  81 #define B_PCH_SATA_PCISTS_CAP_LIST          BIT4  // Capabilities List
  82 #define B_PCH_SATA_PCISTS_ITNS              BIT3  // Interrupt Status
  83
  84 #define R_PCH_SATA_RID                      0x08  // Revision ID (8 bits)
  85
  86 #define R_PCH_SATA_PI_REGISTER              0x09  // Programming Interface (8 bits)
  87 #define B_PCH_SATA_PI_REGISTER_SNC          BIT3  // Secondary Mode Native Capable
  88 #define B_PCH_SATA_PI_REGISTER_SNE          BIT2  // Secondary Mode Native Enable
  89 #define B_PCH_SATA_PI_REGISTER_PNC          BIT1  // Primary Mode Native Capable
  90 #define B_PCH_SATA_PI_REGISTER_PNE          BIT0  // Primary Mode Native Enable
  91
  92 #define R_PCH_SATA_CC                       0x0A  // Class Code
  93 #define B_PCH_SATA_CC_BCC                   0xFF00 // Base Class Code
  94 #define B_PCH_SATA_CC_SCC                   0x00FF // Sub Class Code
  95 #define V_PCH_SATA_CC_SCC_IDE               0x01
  96 #define V_PCH_SATA_CC_SCC_AHCI              0x06
  97 #define V_PCH_SATA_CC_SCC_RAID              0x04
  98
  99 #define R_PCH_SATA_CLS                      0x0C  // Cache Line Size (8 bits)
 100 #define B_PCH_SATA_CLS                      0xFF
 101
 102 #define R_PCH_SATA_MLT                      0x0D  // Master Latency Timer (8 bits)
 103 #define B_PCH_SATA_MLT                      0xFF
 104
 105 #define R_PCH_SATA_HTYPE                    0x0E  // Header Type
 106 #define B_PCH_SATA_HTYPE_MFD                BIT7  // Multi-function Device
 107 #define B_PCH_SATA_HTYPE_HL                 0x7F  // Header Layout
 108
 109 #define R_PCH_SATA_PCMD_BAR                 0x10  // Primary Command Block Base Address
 110 #define B_PCH_SATA_PCMD_BAR_BA              0x0000FFF8 // Base Address
 111 #define B_PCH_SATA_PCMD_BAR_RTE             BIT0  // Resource Type Indicator
 112
 113 #define R_PCH_SATA_PCTL_BAR                 0x14  // Primary Control Block Base Address
 114 #define B_PCH_SATA_PCTL_BAR_BA              0x0000FFFC // Base Address
 115 #define B_PCH_SATA_PCTL_BAR_RTE             BIT0  // Resource Type Indicator
 116
 117 #define R_PCH_SATA_SCMD_BAR                 0x18  // Secondary Command Block Base Address
 118 #define B_PCH_SATA_SCMD_BAR_BA              0x0000FFF8 // Base Address
 119 #define B_PCH_SATA_SCMD_BAR_RTE             BIT0  // Resource Type Indicator
 120
 121 #define R_PCH_SATA_SCTL_BAR                 0x1C  // Secondary Control Block Base Address
 122 #define B_PCH_SATA_SCTL_BAR_BA              0x0000FFFC // Base Address
 123 #define B_PCH_SATA_SCTL_BAR_RTE             BIT0  // Resource Type Indicator
 124
 125 #define R_PCH_SATA_LBAR                     0x20  // Legacy IDE Base Address / AHCI Index Data Pair Base Address
 126 #define B_PCH_SATA_LBAR_BA                  0x0000FFE0 // Base Address
 127 #define B_PCH_SATA_LBAR_BA4                 BIT4  // Base Address 4
 128 #define B_PCH_SATA_LBAR_RTE                 BIT0  // Resource Type Indicator
 129
 130 #define R_PCH_SATA_SIDPBA                   0x24  // Serial ATA Index Data Pair Base Address
 131 #define R_PCH_SATA_ABAR                     0x24  // AHCI Base Address
 132 #define B_PCH_SATA_ABAR_BA                  0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01)
 133 #define V_PCH_SATA_ABAR_LENGTH              0x800 // AHCI Memory Length (When CC.SCC not equal 0x01)
 134 #define N_PCH_SATA_ABAR_ALIGNMENT           11    // AHCI Base Address Alignment (When CC.SCC not equal 0x01)
 135 #define B_PCH_SATA_SIDPBA_BA                0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01)
 136 #define V_PCH_SATA_SIDPBA_LENGTH            0x10  // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01)
 137 #define N_PCH_SATA_SIDPBA_ALIGNMENT         4     // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01)
 138 #define B_PCH_SATA_ABAR_PF                  BIT3  // Prefetchable
 139 #define B_PCH_SATA_ABAR_TP                  (BIT2 | BIT1) // Type
 140 #define B_PCH_SATA_ABAR_RTE                 BIT0  // Resource Type Indicator
 141
 142 #define R_PCH_SATA_SS                       0x2C  // Sub System Identifiers
 143 #define B_PCH_SATA_SS_SSID                  0xFFFF0000 // Subsystem ID
 144 #define B_PCH_SATA_SS_SSVID                 0x0000FFFF // Subsystem Vendor ID
 145
 146 #define R_PCH_SATA_AHCI_CAP_PTR             0x34  // Capabilities Pointer (8 bits)
 147 #define B_PCH_SATA_AHCI_CAP_PTR             0xFF
 148
 149 #define R_PCH_SATA_INTR                     0x3C  // Interrupt Information
 150 #define B_PCH_SATA_INTR_IPIN                0xFFFF0000 // Interrupt Pin
 151 #define B_PCH_SATA_INTR_ILINE               0x0000FFFF // Interrupt Line
 152
 153 #define R_PCH_SATA_PMCS                     0x74  // PCI Power Management Control and Status
 154 #define B_PCH_SATA_PMCS_PMES                BIT15 // PME Status
 155 #define B_PCH_SATA_PMCS_PMEE                BIT8  // PME Enable
 156 #define B_PCH_SATA_PMCS_NSFRST              BIT3  // No Soft Reset
 157 #define V_PCH_SATA_PMCS_NSFRST_1            0x01
 158 #define V_PCH_SATA_PMCS_NSFRST_0            0x00
 159 #define B_PCH_SATA_PMCS_PS                  (BIT1 | BIT0) // Power State
 160 #define V_PCH_SATA_PMCS_PS_3                0x03
 161 #define V_PCH_SATA_PMCS_PS_0                0x00
 162
 163 #define R_PCH_SATA_MAP                      0x90  // Port Mapping Register
 164 #define B_PCH_SATA_MAP_SPD                  (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
 165 #define B_PCH_SATA_PORT6_DISABLED           BIT14
 166 #define B_PCH_SATA_PORT5_DISABLED           BIT13
 167 #define B_PCH_SATA_PORT4_DISABLED           BIT12
 168 #define B_PCH_SATA_PORT3_DISABLED           BIT11
 169 #define B_PCH_SATA_PORT2_DISABLED           BIT10
 170 #define B_PCH_SATA_PORT1_DISABLED           BIT9
 171 #define B_PCH_SATA_PORT0_DISABLED           BIT8
 172 #define B_PCH_SATA_MAP_SMS_MASK             (BIT7 | BIT6) // SATA Mode Select
 173 #define V_PCH_SATA_MAP_SMS_IDE              0x00
 174 #define V_PCH_SATA_MAP_SMS_AHCI             0x40
 175 #define V_PCH_SATA_MAP_SMS_RAID             0x80
 176 #define B_PCH_SATA_PORT_TO_CONTROLLER_CFG   BIT5  // SATA Port-to-Controller Configuration
 177
 178 #define R_PCH_SATA_PCS                      0x92  // Port Control and Status
 179 #define S_PCH_SATA_PCS                      0x2
 180 #define B_PCH_SATA_PCS_OOB_RETRY            BIT15 // OOB Retry Mode
 181 #define B_PCH_SATA_PCS_PORT6_DET            BIT14 // Port 6 Present
 182 #define B_PCH_SATA_PCS_PORT5_DET            BIT13 // Port 5 Present
 183 #define B_PCH_SATA_PCS_PORT4_DET            BIT12 // Port 4 Present
 184 #define B_PCH_SATA_PCS_PORT3_DET            BIT11 // Port 3 Present
 185 #define B_PCH_SATA_PCS_PORT2_DET            BIT10 // Port 2 Present
 186 #define B_PCH_SATA_PCS_PORT1_DET            BIT9  // Port 1 Present
 187 #define B_PCH_SATA_PCS_PORT0_DET            BIT8  // Port 0 Present
 188 #define B_PCH_SATA_PCS_PORT5_EN             BIT5  // Port 5 Enabled
 189 #define B_PCH_SATA_PCS_PORT4_EN             BIT4  // Port 4 Enabled
 190 #define B_PCH_SATA_PCS_PORT3_EN             BIT3  // Port 3 Enabled
 191 #define B_PCH_SATA_PCS_PORT2_EN             BIT2  // Port 2 Enabled
 192 #define B_PCH_SATA_PCS_PORT1_EN             BIT1  // Port 1 Enabled
 193 #define B_PCH_SATA_PCS_PORT0_EN             BIT0  // Port 0 Enabled
 194
 195 #define R_PCH_SATA_AHCI_PI                  0x0C  // Ports Implemented
 196 #define B_PCH_SATA_PORT_MASK                0x3F
 197 #define B_PCH_SATA_PORT5_IMPLEMENTED        BIT5  // Port 5 Implemented
 198 #define B_PCH_SATA_PORT4_IMPLEMENTED        BIT4  // Port 4 Implemented
 199 #define B_PCH_SATA_PORT3_IMPLEMENTED        BIT3  // Port 3 Implemented
 200 #define B_PCH_SATA_PORT2_IMPLEMENTED        BIT2  // Port 2 Implemented
 201 #define B_PCH_SATA_PORT1_IMPLEMENTED        BIT1  // Port 1 Implemented
 202 #define B_PCH_SATA_PORT0_IMPLEMENTED        BIT0  // Port 0 Implemented
 203
 204 #define R_PCH_SATA_AHCI_P0SSTS              0x128 // Port 0 Serial ATA Status
 205 #define R_PCH_SATA_AHCI_P1SSTS              0x1A8 // Port 1 Serial ATA Status
 206 #define B_PCH_SATA_AHCI_PXSSTS_IPM          0x00000F00 // Interface Power Management
 207 #define B_PCH_SATA_AHCI_PXSSTS_IPM_0        0x00000000
 208 #define B_PCH_SATA_AHCI_PXSSTS_IPM_1        0x00000100
 209 #define B_PCH_SATA_AHCI_PXSSTS_IPM_2        0x00000200
 210 #define B_PCH_SATA_AHCI_PXSSTS_IPM_6        0x00000600
 211 #define B_PCH_SATA_AHCI_PXSSTS_SPD          0x000000F0 // Current Interface Speed
 212 #define B_PCH_SATA_AHCI_PXSSTS_SPD_0        0x00000000
 213 #define B_PCH_SATA_AHCI_PXSSTS_SPD_1        0x00000010
 214 #define B_PCH_SATA_AHCI_PXSSTS_SPD_2        0x00000020
 215 #define B_PCH_SATA_AHCI_PXSSTS_SPD_3        0x00000030
 216 #define B_PCH_SATA_AHCI_PXSSTS_DET          0x0000000F // Device Detection
 217 #define B_PCH_SATA_AHCI_PXSSTS_DET_0        0x00000000
 218 #define B_PCH_SATA_AHCI_PXSSTS_DET_1        0x00000001
 219 #define B_PCH_SATA_AHCI_PXSSTS_DET_3        0x00000003
 220 #define B_PCH_SATA_AHCI_PXSSTS_DET_4        0x00000004
 221
 222 //
 223 // Macros of VLV capabilities for SATA controller which are used by SATA controller driver
 224 //
 225 //
 226 //
 227 // Define the individual capabilities of each SATA controller
 228 //
 229 #define PCH_SATA_MAX_CONTROLLERS            1     // Max SATA controllers number supported
 230 #define PCH_SATA_MAX_DEVICES                2     // Max SATA devices number of single SATA channel
 231 #define PCH_IDE_MAX_CHANNELS                2     // Max IDE channels number of single SATA controller
 232 #define PCH_IDE_MAX_DEVICES                 2     // Max IDE devices number of single SATA channel
 233 #define PCH_AHCI_MAX_PORTS                  2     // Max number of SATA ports in VLV
 234 #define PCH_IDE_MAX_PORTS                   2     // Max number of IDE ports in VLV
 235
 236 //
 237 // GPIOS_14 SATA0GP is the SATA port 0 reset pin.
 238 //
 239 #define PCH_GPIO_SATA_PORT0_RESET           14
 240 //
 241 // GPIOS_15 SATA1GP is the SATA port 1 reset pin.
 242 //
 243 #define PCH_GPIO_SATA_PORT1_RESET           15
 244
 245 #endif