Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h

   1 /**
   2
   3 Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchRegsSmbus.h
  11
  12   @brief
  13   Register names for VLV Smbus Device.
  14
  15   Conventions:
  16
  17   - Prefixes:
  18     Definitions beginning with "R_" are registers
  19     Definitions beginning with "B_" are bits within registers
  20     Definitions beginning with "V_" are meaningful values of bits within the registers
  21     Definitions beginning with "S_" are register sizes
  22     Definitions beginning with "N_" are the bit position
  23   - In general, PCH registers are denoted by "_PCH_" in register names
  24   - Registers / bits that are different between PCH generations are denoted by
  25     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  26   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  27     at the end of the register/bit names
  28   - Registers / bits of new devices introduced in a PCH generation will be just named
  29     as "_PCH_" without <generation_name> inserted.
  30
  31 **/
  32 #ifndef _PCH_REGS_SMBUS_H_
  33 #define _PCH_REGS_SMBUS_H_
  34
  35 ///
  36 /// SMBus Controller Registers (D31:F3)
  37 ///
  38 #define PCI_DEVICE_NUMBER_PCH_SMBUS        31
  39 #define PCI_FUNCTION_NUMBER_PCH_SMBUS      3
  40
  41 #define R_PCH_SMBUS_VENDOR_ID              0x00  // Vendor ID
  42 #define V_PCH_SMBUS_VENDOR_ID              V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
  43
  44 #define R_PCH_SMBUS_DEVICE_ID              0x02  // Device ID
  45 #define V_PCH_SMBUS_DEVICE_ID              0x0F12
  46
  47 #define R_PCH_SMBUS_PCICMD                 0x04  // CMD register enables/disables, Memory/IO space access and interrupt
  48 #define B_PCH_SMBUS_PCICMD_INTR_DIS        BIT10 // Interrupt Disable
  49 #define B_PCH_SMBUS_PCICMD_FBE             BIT9  // FBE - reserved as '0'
  50 #define B_PCH_SMBUS_PCICMD_SERR_EN         BIT8  // SERR Enable - reserved as '0'
  51 #define B_PCH_SMBUS_PCICMD_WCC             BIT7  // Wait Cycle Control - reserved as '0'
  52 #define B_PCH_SMBUS_PCICMD_PER             BIT6  // Parity Error - reserved as '0'
  53 #define B_PCH_SMBUS_PCICMD_VPS             BIT5  // VGA Palette Snoop - reserved as '0'
  54 #define B_PCH_SMBUS_PCICMD_PMWE            BIT4  // Postable Memory Write Enable - reserved as '0'
  55 #define B_PCH_SMBUS_PCICMD_SCE             BIT3  // Special Cycle Enable - reserved as '0'
  56 #define B_PCH_SMBUS_PCICMD_BME             BIT2  // Bus Master Enable - reserved as '0'
  57 #define B_PCH_SMBUS_PCICMD_MSE             BIT1  // Memory Space Enable
  58 #define B_PCH_SMBUS_PCICMD_IOSE            BIT0  // I/O Space Enable
  59
  60 #define R_PCH_SMBUS_BASE                   0x20  // The I/O memory bar
  61 #define B_PCH_SMBUS_BASE_BAR               0x0000FFE0 // Base Address
  62 #define B_PCH_SMBUS_BASE_IOSI              BIT0  // IO Space Indicator
  63
  64 #define R_PCH_SMBUS_SVID                   0x2C  // Subsystem Vendor ID
  65 #define B_PCH_SMBUS_SVID                   0xFFFF // Subsystem Vendor ID
  66
  67 //
  68 // SMBus I/O Registers
  69 //
  70 #define R_PCH_SMBUS_HSTS                   0x00  // Host Status Register R/W
  71 #define B_PCH_SMBUS_HSTS_ALL               0xFF
  72 #define B_PCH_SMBUS_BYTE_DONE_STS          BIT7  // Byte Done Status
  73 #define B_PCH_SMBUS_IUS                    BIT6  // In Use Status
  74 #define B_PCH_SMBUS_SMBALERT_STS           BIT5  // SMBUS Alert
  75 #define B_PCH_SMBUS_FAIL                   BIT4  // Failed
  76 #define B_PCH_SMBUS_BERR                   BIT3  // Bus Error
  77 #define B_PCH_SMBUS_DERR                   BIT2  // Device Error
  78 #define B_PCH_SMBUS_ERRORS                 (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
  79 #define B_PCH_SMBUS_INTR                   BIT1  // Interrupt
  80 #define B_PCH_SMBUS_HBSY                   BIT0  // Host Busy
  81
  82 #define R_PCH_SMBUS_HCTL                   0x02  // Host Control Register R/W
  83 #define B_PCH_SMBUS_PEC_EN                 BIT7  // Packet Error Checking Enable
  84 #define B_PCH_SMBUS_START                  BIT6  // Start
  85 #define B_PCH_SMBUS_LAST_BYTE              BIT5  // Last Byte
  86 #define B_PCH_SMBUS_SMB_CMD                0x1C  // SMB Command
  87 #define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS  0x1C  // Block Process
  88 #define V_PCH_SMBUS_SMB_CMD_IIC_READ       0x18  // I2C Read
  89 #define V_PCH_SMBUS_SMB_CMD_BLOCK          0x14  // Block
  90 #define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL   0x10  // Process Call
  91 #define V_PCH_SMBUS_SMB_CMD_WORD_DATA      0x0C  // Word Data
  92 #define V_PCH_SMBUS_SMB_CMD_BYTE_DATA      0x08  // Byte Data
  93 #define V_PCH_SMBUS_SMB_CMD_BYTE           0x04  // Byte
  94 #define V_PCH_SMBUS_SMB_CMD_QUICK          0x00  // Quick
  95 #define B_PCH_SMBUS_KILL                   BIT1  // Kill
  96 #define B_PCH_SMBUS_INTREN                 BIT0  // Interrupt Enable
  97
  98 #define R_PCH_SMBUS_HCMD                   0x03  // Host Command Register R/W
  99 #define B_PCH_SMBUS_HCMD                   0xFF  // Command to be transmitted
 100
 101 #define R_PCH_SMBUS_TSA                    0x04  // Transmit Slave Address Register R/W
 102 #define B_PCH_SMBUS_ADDRESS                0xFE  // 7-bit address of the targeted slave
 103 #define B_PCH_SMBUS_RW_SEL                 BIT0  // Direction of the host transfer, 1 = read, 0 = write
 104 #define B_PCH_SMBUS_RW_SEL_READ            0x01  // Read
 105 #define B_PCH_SMBUS_RW_SEL_WRITE           0x00  // Write
 106 //
 107 #define R_PCH_SMBUS_HD0                    0x05  // Data 0 Register R/W
 108 #define R_PCH_SMBUS_HD1                    0x06  // Data 1 Register R/W
 109 #define R_PCH_SMBUS_HBD                    0x07  // Host Block Data Register R/W
 110 #define R_PCH_SMBUS_PEC                    0x08  // Packet Error Check Data Register R/W
 111
 112 #define R_PCH_SMBUS_RSA                    0x09  // Receive Slave Address Register R/W
 113 #define B_PCH_SMBUS_SLAVE_ADDR             0x7F  // TCO slave address (Not used, reserved)
 114
 115 #define R_PCH_SMBUS_SD                     0x0A  // Receive Slave Data Register R/W
 116
 117 #define R_PCH_SMBUS_AUXS                   0x0C  // Auxiliary Status Register R/WC
 118 #define B_PCH_SMBUS_CRCE                   BIT0  // CRC Error
 119 //
 120 #define R_PCH_SMBUS_AUXC                   0x0D  // Auxiliary Control Register R/W
 121 #define B_PCH_SMBUS_E32B                   BIT1  // Enable 32-byte Buffer
 122 #define B_PCH_SMBUS_AAC                    BIT0  // Automatically Append CRC
 123
 124 #define R_PCH_SMBUS_SMLC                   0x0E  // SMLINK Pin Control Register R/W
 125 #define B_PCH_SMBUS_SMLINK_CLK_CTL         BIT2  // Not supported
 126 #define B_PCH_SMBUS_SMLINK1_CUR_STS        BIT1  // Not supported
 127 #define B_PCH_SMBUS_SMLINK0_CUR_STS        BIT0  // Not supported
 128
 129
 130 #define R_PCH_SMBUS_SMBC                   0x0F  // SMBus Pin Control Register R/W
 131 #define B_PCH_SMBUS_SMBCLK_CTL             BIT2  // SMBCLK Control
 132 #define B_PCH_SMBUS_SMBDATA_CUR_STS        BIT1  // SMBDATA Current Status
 133 #define B_PCH_SMBUS_SMBCLK_CUR_STS         BIT0  // SMBCLK Current Status
 134
 135 #define R_PCH_SMBUS_SSTS                   0x10  // Slave Status Register R/WC
 136 #define B_PCH_SMBUS_HOST_NOTIFY_STS        BIT0  // Host Notify Status
 137
 138 #define R_PCH_SMBUS_SCMD                   0x11  // Slave Command Register R/W
 139 #define B_PCH_SMBUS_SMBALERT_DIS           BIT2  // Not supported
 140 #define B_PCH_SMBUS_HOST_NOTIFY_WKEN       BIT1  // Host Notify Wake Enable
 141 #define B_PCH_SMBUS_HOST_NOTIFY_INTREN     BIT0  // Host Notify Interrupt Enable
 142
 143 #define R_PCH_SMBUS_NDA                    0x14  // Notify Device Address Register RO
 144 #define B_PCH_SMBUS_DEVICE_ADDRESS         0xFE  // Device Address
 145
 146 #define R_PCH_SMBUS_NDLB                   0x16  // Notify Data Low Byte Register RO
 147 #define R_PCH_SMBUS_NDHB                   0x17  // Notify Data High Byte Register RO
 148
 149 #endif