Add definitions for Protected Region 1 register.
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsSpi.h
1 /**
2
3 Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved
4
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13
14
15 @file
16 PchRegsSpi.h
17
18 @brief
19 Register names for PCH SPI device.
20
21 Conventions:
22
23 - Prefixes:
24 Definitions beginning with "R_" are registers
25 Definitions beginning with "B_" are bits within registers
26 Definitions beginning with "V_" are meaningful values of bits within the registers
27 Definitions beginning with "S_" are register sizes
28 Definitions beginning with "N_" are the bit position
29 - In general, PCH registers are denoted by "_PCH_" in register names
30 - Registers / bits that are different between PCH generations are denoted by
31 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
32 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
33 at the end of the register/bit names
34 - Registers / bits of new devices introduced in a PCH generation will be just named
35 as "_PCH_" without <generation_name> inserted.
36
37 **/
38 #ifndef _PCH_REGS_SPI_H_
39 #define _PCH_REGS_SPI_H_
40
41 ///
42 /// SPI Host Interface Registers
43 ///
44
45 #define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits)
46 #define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
47 #define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid
48 #define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
49 #define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress
50 #define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size
51 #define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes
52 #define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes
53 #define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes
54 #define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes
55 #define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log
56 #define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error
57 #define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done
58
59 #define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register
60 #define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable
61 #define B_PCH_SPI_PR0_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
62 #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
63 #define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
64
65 #define R_PCH_SPI_PR1 0x78 // Protected Region 1 Register
66 #define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable
67 #define B_PCH_SPI_PR1_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
68 #define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
69 #define B_PCH_SPI_PR1_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
70
71 #define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)
72 #define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
73 #define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
74
75 #define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration
76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
77 #define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
78 #define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) // Opcode Type 5 Mask
79 #define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask
80 #define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) // Opcode Type 3 Mask
81 #define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
82 #define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask
83 #define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask
84 #define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address
85 #define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address
86 #define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type
87 #define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type
88
89 #define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits)
90 #define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits)
91
92 #define R_PCH_SPI_IND_LOCK 0xA4 // Indvidual Lock
93 #define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown
94
95
96 #define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits)
97 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
98 #define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map
99 #define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component
100 #define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region
101 #define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master
102 #define V_PCH_SPI_FDOC_FDSS_VLVS 0x4000 // Soft Straps
103 #define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index
104
105 #define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits)
106
107 #define R_PCH_SPI_BCR 0xFC // BIOS Control Register
108 #define S_PCH_SPI_BCR 1
109 #define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable
110 #define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
111 #define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable
112 #define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable
113 #define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable
114 #define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)
115 #define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD)
116 #define N_PCH_SPI_BCR_BLE 1
117 #define N_PCH_SPI_BCR_BIOSWE 0
118
119 //
120 // Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
121 //
122 #define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature
123 #define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
124
125 #endif