Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h

   1 /**
   2 **/
   3 /**
   4
   5 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9
  10
  11   @file
  12   PchPlatformPolicy.h
  13
  14   @brief
  15   PCH policy PPI produced by a platform driver specifying various
  16   expected PCH settings. This PPI is consumed by the PCH PEI modules.
  17
  18 **/
  19 #ifndef PCH_PLATFORM_POLICY_H_
  20 #define PCH_PLATFORM_POLICY_H_
  21 //
  22 // External include files do NOT need to be explicitly specified in real EDKII
  23 // environment
  24 //
  25
  26
  27 #include "PchRegs.h"
  28
  29 //
  30 #define PCH_PLATFORM_POLICY_PPI_GUID \
  31   { \
  32     0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
  33   }
  34
  35 extern EFI_GUID                         gPchPlatformPolicyPpiGuid;
  36
  37 ///
  38 /// Forward reference for ANSI C compatibility
  39 ///
  40 typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
  41
  42 ///
  43 /// PPI revision number
  44 /// Any backwards compatible changes to this PPI will result in an update in the revision number
  45 /// Major changes will require publication of a new PPI
  46 ///
  47 /// Revision 1:    Original version
  48 ///
  49 #define PCH_PLATFORM_POLICY_PPI_REVISION_1  1
  50 #define PCH_PLATFORM_POLICY_PPI_REVISION_2  2
  51 #define PCH_PLATFORM_POLICY_PPI_REVISION_3  3
  52 #define PCH_PLATFORM_POLICY_PPI_REVISION_4  4
  53 #define PCH_PLATFORM_POLICY_PPI_REVISION_5  5
  54 //
  55 // Generic definitions for device enabling/disabling used by PCH code.
  56 //
  57 #define PCH_DEVICE_ENABLE   1
  58 #define PCH_DEVICE_DISABLE  0
  59
  60 typedef struct {
  61   UINT8  ThermalDataReportEnable  : 1;   // OBSOLETE from Revision 5 !!! DO NOT USE !!!
  62   UINT8  MchTempReadEnable        : 1;
  63   UINT8  PchTempReadEnable        : 1;
  64   UINT8  CpuEnergyReadEnable      : 1;
  65   UINT8  CpuTempReadEnable        : 1;
  66   UINT8  Cpu2TempReadEnable       : 1;
  67   UINT8  TsOnDimmEnable           : 1;
  68   UINT8  Dimm1TempReadEnable      : 1;
  69
  70   UINT8  Dimm2TempReadEnable      : 1;
  71   UINT8  Dimm3TempReadEnable      : 1;
  72   UINT8  Dimm4TempReadEnable      : 1;
  73   UINT8  Rsvdbits                 : 5;
  74 } PCH_THERMAL_REPORT_CONTROL;
  75 //
  76 // ---------------------------- HPET Config -----------------------------
  77 //
  78 typedef struct {
  79   BOOLEAN Enable; /// Determines if enable HPET function
  80   UINT32  Base;   /// The HPET base address
  81 } PCH_HPET_CONFIG;
  82
  83
  84 ///
  85 /// ---------------------------- SATA Config -----------------------------
  86 ///
  87 typedef enum {
  88   PchSataModeIde,
  89   PchSataModeAhci,
  90   PchSataModeRaid,
  91   PchSataModeMax
  92 } PCH_SATA_MODE;
  93
  94 ///
  95 /// ---------------------------- PCI Express Config -----------------------------
  96 ///
  97 typedef enum {
  98   PchPcieAuto,
  99   PchPcieGen1,
 100   PchPcieGen2
 101 } PCH_PCIE_SPEED;
 102
 103 typedef struct {
 104   PCH_PCIE_SPEED  PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
 105 } PCH_PCIE_CONFIG;
 106
 107 ///
 108 /// ---------------------------- IO APIC Config -----------------------------
 109 ///
 110 typedef struct {
 111   UINT8 IoApicId;
 112 } PCH_IOAPIC_CONFIG;
 113
 114 ///
 115 /// --------------------- Low Power Input Output Config ------------------------
 116 ///
 117 typedef struct {
 118   UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled
 119   UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled
 120   UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled
 121   UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled
 122   UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled
 123   UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled
 124   UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled
 125   UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled
 126   UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled
 127   UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled
 128   UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled
 129   UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled
 130   UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled
 131   UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled
 132   UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled
 133   UINT8                   Rsvdbits              : 2;
 134 } PEI_PCH_LPSS_CONFIG;
 135
 136 ///
 137 /// ------------ General PCH Platform Policy PPI definition ------------
 138 ///
 139 struct _PCH_PLATFORM_POLICY_PPI {
 140   UINT8                         Revision;
 141   UINT8                         BusNumber;  // Bus Number of the PCH device
 142   UINT32                        SpiBase;    // SPI Base Address.
 143   UINT32                        PmcBase;    // PMC Base Address.
 144   UINT32                        SmbmBase;   // SMB Memory Base Address.
 145   UINT32                        IoBase;     // IO Base Address.
 146   UINT32                        IlbBase;    // Intel Legacy Block Base Address.
 147   UINT32                        PUnitBase;  // PUnit Base Address.
 148   UINT32                        Rcba;       // Root Complex Base Address.
 149   UINT32                        MphyBase;   // MPHY Base Address.
 150   UINT16                        AcpiBase;   // ACPI I/O Base address.
 151   UINT16                        GpioBase;   // GPIO Base address
 152   PCH_HPET_CONFIG               *HpetConfig;
 153   PCH_SATA_MODE                 SataMode;
 154   PCH_PCIE_CONFIG               *PcieConfig;
 155   PCH_IOAPIC_CONFIG             *IoApicConfig;
 156   PEI_PCH_LPSS_CONFIG           *LpssConfig;
 157   BOOLEAN                       EnableRmh;      // Determines if enable USB RMH function
 158   BOOLEAN                       EhciPllCfgEnable;
 159 };
 160
 161 #endif