Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h

   1 /**
   2 **/
   3 /**
   4
   5 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9
  10
  11   @file
  12   Spi.h
  13
  14   @brief
  15   This file defines the EFI SPI PPI which implements the
  16   Intel(R) PCH SPI Host Controller Compatibility Interface.
  17
  18 **/
  19 #ifndef _PEI_SDHC_H_
  20 #define _PEI_SDHC_H_
  21
  22
  23
  24 //
  25 #define PEI_SDHC_PPI_GUID \
  26   {  \
  27     0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \
  28   }
  29 typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;
  30
  31 #define EFI_SD_HOST_IO_PROTOCOL_REVISION_01          0x01
  32
  33 typedef enum {
  34   ResponseNo = 0,
  35   ResponseR1,
  36   ResponseR1b,
  37   ResponseR2,
  38   ResponseR3,
  39   ResponseR4,
  40   ResponseR5,
  41   ResponseR5b,
  42   ResponseR6,
  43   ResponseR7
  44 } RESPONSE_TYPE;
  45
  46 typedef enum {
  47   NoData = 0,
  48   InData,
  49   OutData
  50 } TRANSFER_TYPE;
  51
  52 typedef enum {
  53   Reset_Auto = 0,
  54   Reset_DAT,
  55   Reset_CMD,
  56   Reset_DAT_CMD,
  57   Reset_All
  58 } RESET_TYPE;
  59
  60
  61
  62 typedef enum {
  63   SDMA = 0,
  64   ADMA2,
  65   PIO
  66 } DMA_MOD;
  67
  68 typedef struct {
  69   UINT32  HighSpeedSupport:    1;  //High speed supported
  70   UINT32  V18Support:          1;  //1.8V supported
  71   UINT32  V30Support:          1;  //3.0V supported
  72   UINT32  V33Support:          1;  //3.3V supported
  73   UINT32  Reserved0:           4;
  74   UINT32  BusWidth4:           1;  // 4 bit width
  75   UINT32  BusWidth8:           1;  // 8 bit width
  76   UINT32  Reserved1:           6;
  77   UINT32  SDMASupport:         1;
  78   UINT32  ADMA2Support:        1;
  79   UINT32  DmaMode:             2;
  80   UINT32  Reserved2:           12;
  81   UINT32  BoundarySize;
  82 }HOST_CAPABILITY;
  83
  84
  85 #define PCI_SUBCLASS_SD_HOST_CONTROLLER   0x05
  86 #define PCI_IF_STANDARD_HOST_NO_DMA       0x00
  87 #define PCI_IF_STANDARD_HOST_SUPPORT_DMA  0x01
  88
  89 //
  90 //MMIO Registers definition for MMC/SDIO controller
  91 //
  92 #define  MMIO_DMAADR                     0x00
  93 #define  MMIO_BLKSZ                      0x04
  94 #define  MMIO_BLKCNT                     0x06
  95 #define  MMIO_CMDARG                     0x08
  96 #define  MMIO_XFRMODE                    0x0C
  97 #define  MMIO_SDCMD                      0x0E
  98 #define  MMIO_RESP                       0x10
  99 #define  MMIO_BUFDATA                    0x20
 100 #define  MMIO_PSTATE                     0x24
 101 #define  MMIO_HOSTCTL                    0x28
 102 #define  MMIO_PWRCTL                     0x29
 103 #define  MMIO_BLKGAPCTL                  0x2A
 104 #define  MMIO_WAKECTL                    0x2B
 105 #define  MMIO_CLKCTL                     0x2C
 106 #define  MMIO_TOCTL                      0x2E
 107 #define  MMIO_SWRST                      0x2F
 108 #define  MMIO_NINTSTS                    0x30
 109 #define  MMIO_ERINTSTS                   0x32
 110 #define  MMIO_NINTEN                     0x34
 111 #define  MMIO_ERINTEN                    0x36
 112 #define  MMIO_NINTSIGEN                  0x38
 113 #define  MMIO_ERINTSIGEN                 0x3A
 114 #define  MMIO_AC12ERRSTS                 0x3C
 115 #define  MMIO_HOST_CTL2                  0x3E //hphang <- New in VLV2
 116 #define  MMIO_CAP                        0x40
 117 #define  MMIO_CAP2                       0x44 //hphang <- New in VLV2
 118 #define  MMIO_MCCAP                      0x48
 119 #define  MMIO_FORCEEVENTCMD12ERRSTAT     0x50 //hphang <- New in VLV2
 120 #define  MMIO_FORCEEVENTERRINTSTAT       0x52 //hphang <- New in VLV2
 121 #define  MMIO_ADMAERRSTAT                0x54 //hphang <- New in VLV2
 122 #define  MMIO_ADMASYSADDR                0x58 //hphang <- New in VLV2
 123 #define  MMIO_PRESETVALUE0               0x60 //hphang <- New in VLV2
 124 #define  MMIO_PRESETVALUE1               0x64 //hphang <- New in VLV2
 125 #define  MMIO_PRESETVALUE2               0x68 //hphang <- New in VLV2
 126 #define  MMIO_PRESETVALUE3               0x6C //hphang <- New in VLV2
 127 #define  MMIO_BOOTTIMEOUTCTRL            0x70 //hphang <- New in VLV2
 128 #define  MMIO_DEBUGSEL                   0x74 //hphang <- New in VLV2
 129 #define  MMIO_SHAREDBUS                  0xE0 //hphang <- New in VLV2
 130 #define  MMIO_SPIINTSUP                  0xF0 //hphang <- New in VLV2
 131 #define  MMIO_SLTINTSTS                  0xFC
 132 #define  MMIO_CTRLRVER                   0xFE
 133 #define  MMIO_SRST                       0x1FC
 134
 135 typedef
 136 EFI_STATUS
 137 (EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (
 138   IN  PEI_SD_CONTROLLER_PPI       *This,
 139   IN   UINT16                     CommandIndex,
 140   IN   UINT32                     Argument,
 141   IN   TRANSFER_TYPE              DataType,
 142   IN   UINT8                      *Buffer, OPTIONAL
 143   IN   UINT32                     BufferSize,
 144   IN   RESPONSE_TYPE              ResponseType,
 145   IN   UINT32                     TimeOut,
 146   OUT  UINT32                     *ResponseData OPTIONAL
 147   );
 148
 149 /*++
 150
 151   Routine Description:
 152     Set max clock frequency of the host, the actual frequency
 153     may not be the same as MaxFrequency. It depends on
 154     the max frequency the host can support, divider, and host
 155     speed mode.
 156
 157   Arguments:
 158     This           - Pointer to EFI_SD_HOST_IO_PROTOCOL
 159     MaxFrequency   - Max frequency in HZ
 160
 161   Returns:
 162     EFI_SUCCESS
 163     EFI_TIMEOUT
 164 --*/
 165 typedef
 166 EFI_STATUS
 167 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (
 168   IN  PEI_SD_CONTROLLER_PPI      *This,
 169   IN  UINT32                     MaxFrequency
 170   );
 171
 172 /*++
 173
 174   Routine Description:
 175     Set bus width of the host
 176
 177   Arguments:
 178     This       - Pointer to EFI_SD_HOST_IO_PROTOCOL
 179     BusWidth   - Bus width in 1, 4, 8 bits
 180
 181   Returns:
 182     EFI_SUCCESS
 183     EFI_INVALID_PARAMETER
 184
 185 --*/
 186 typedef
 187 EFI_STATUS
 188 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (
 189   IN  PEI_SD_CONTROLLER_PPI      *This,
 190   IN  UINT32                     BusWidth
 191   );
 192
 193 /*++
 194
 195   Routine Description:
 196     Set Host mode in DDR
 197   Arguments:
 198     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 199     SetHostDdrMode   - True for DDR Mode set, false for normal mode
 200
 201   Returns:
 202     EFI_SUCCESS
 203     EFI_INVALID_PARAMETER
 204
 205 --*/
 206 typedef
 207 EFI_STATUS
 208 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
 209   IN  PEI_SD_CONTROLLER_PPI    *This,
 210   IN  UINT32                     DdrMode
 211   );
 212
 213 /*++
 214
 215   Routine Description:
 216     Set voltage which could supported by the host.
 217     Support 0(Power off the host), 1.8V, 3.0V, 3.3V
 218   Arguments:
 219     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 220     Voltage   - Units in 0.1 V
 221
 222   Returns:
 223     EFI_SUCCESS
 224     EFI_INVALID_PARAMETER
 225
 226 --*/
 227 typedef
 228 EFI_STATUS
 229 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (
 230   IN  PEI_SD_CONTROLLER_PPI      *This,
 231   IN  UINT32                     Voltage
 232   );
 233
 234 /*++
 235
 236   Routine Description:
 237    Reset the host
 238
 239   Arguments:
 240     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 241     ResetAll  - TRUE to reset all
 242
 243   Returns:
 244     EFI_SUCCESS
 245     EFI_TIMEOUT
 246
 247 --*/
 248 typedef
 249 EFI_STATUS
 250 (EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (
 251   IN  PEI_SD_CONTROLLER_PPI      *This,
 252   IN  RESET_TYPE                 ResetType
 253   );
 254
 255 /*++
 256
 257   Routine Description:
 258    Reset the host
 259
 260   Arguments:
 261     This    - Pointer to EFI_SD_HOST_IO_PROTOCOL
 262     Enable  - TRUE to enable, FALSE to disable
 263
 264   Returns:
 265     EFI_SUCCESS
 266     EFI_TIMEOUT
 267
 268 --*/
 269 typedef
 270 EFI_STATUS
 271 (EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (
 272   IN  PEI_SD_CONTROLLER_PPI      *This,
 273   IN  BOOLEAN                    Enable
 274   );
 275
 276 /*++
 277
 278   Routine Description:
 279     Find whether these is a card inserted into the slot. If so
 280     init the host. If not, return EFI_NOT_FOUND.
 281
 282   Arguments:
 283     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 284
 285   Returns:
 286     EFI_SUCCESS
 287     EFI_NOT_FOUND
 288
 289 --*/
 290 typedef
 291 EFI_STATUS
 292 (EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (
 293   IN  PEI_SD_CONTROLLER_PPI      *This
 294   );
 295
 296 /*++
 297
 298   Routine Description:
 299    Set the Block length
 300
 301   Arguments:
 302     This        - Pointer to EFI_SD_HOST_IO_PROTOCOL
 303     BlockLength - card supportes block length
 304
 305   Returns:
 306     EFI_SUCCESS
 307     EFI_TIMEOUT
 308
 309 --*/
 310 typedef
 311 EFI_STATUS
 312 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (
 313   IN  PEI_SD_CONTROLLER_PPI      *This,
 314   IN  UINT32                     BlockLength
 315   );
 316
 317 /*++
 318
 319   Routine Description:
 320    Set the Block length
 321
 322   Arguments:
 323     This        - Pointer to EFI_SD_HOST_IO_PROTOCOL
 324     BlockLength - card supportes block length
 325
 326   Returns:
 327     EFI_SUCCESS
 328     EFI_TIMEOUT
 329
 330 --*/
 331
 332 typedef EFI_STATUS
 333 (EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(
 334   IN  PEI_SD_CONTROLLER_PPI    *This
 335   );
 336
 337 //
 338 // Interface structure for the EFI SD Host I/O Protocol
 339 //
 340 struct _PEI_SD_CONTROLLER_PPI {
 341   UINT32                                           Revision;
 342   HOST_CAPABILITY                                  HostCapability;
 343   EFI_SD_CONTROLLER_PPI_SEND_COMMAND               SendCommand;
 344   EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY        SetClockFrequency;
 345   EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH              SetBusWidth;
 346   EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE           SetHostVoltage;
 347   EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE        SetHostDdrMode;
 348   EFI_SD_CONTROLLER_PPI_RESET_SD_HOST              ResetSdHost;
 349   EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD       EnableAutoStopCmd;
 350   EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST  DetectCardAndInitHost;
 351   EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH           SetBlockLength;
 352   EFI_SD_CONTROLLER_PPI_SETUP_DEVICE               SetupDevice;
 353 };
 354 // Extern the GUID for PPI users.
 355 //
 356 extern EFI_GUID           gPeiSdhcPpiGuid;
 357
 358
 359 #endif