Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h

   1 /*++
   2
   3 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9 Module Name:
  10
  11   Gpio.h
  12
  13 Abstract:
  14
  15 EFI 2.0 PEIM to provide platform specific information to other
  16 modules and to do some platform specific initialization.
  17
  18 --*/
  19
  20 #ifndef _PEI_GPIO_H
  21 #define _PEI_GPIO_H
  22
  23 //#include "Efi.h"
  24 //#include "EfiCommonLib.h"
  25 //#include "Pei.h"
  26 //#include "Numbers.h"
  27
  28 ////
  29 //// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)
  30 ////
  31 //// Field Descriptions:
  32 ////    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.
  33 ////    I/O: Defines whether GPIOs are inputs (I) or outputs (O).
  34 ////         (Note:  Only meaningful for pins used as GPIOs.)
  35 ////    LVL: This field gives you the initial value for "output" GPIO's.
  36 ////         (Note: The output level is dependent upon whether the pin is inverted.)
  37 ////    INV: Defines whether Input GPIOs activation level is inverted.
  38 ////         (Note:  Only affects the level sent to the GPE logic and does not
  39 ////         affect the level read through the GPIO registers.)
  40 ////
  41 //// Notes:
  42 ////    1. BoardID is GPIO [8:38:34]
  43 ////
  44 ////Signal         UsedAs               USE     I/O      LVL     INV
  45 ////--------------------------------------------------------------------------
  46 ////GPIO0           Nonfunction       G     O            H       -
  47 ////GPIO1           SMC_RUNTIME_SCI#    G        I           -       I
  48 ////PIRQE#/GPIO2    Nonfunction G   O   H   -
  49 ////PIRQF#/GPIO3    Nonfunction G   O   H   -
  50 ////PIRQG#/GPIO4    Nonfunction G   O   H   -
  51 ////PIRQH#/GPIO5    Nonfunction G   O   H   -
  52 ////GPIO6   unused  G   O   L   -
  53 ////GPIO7   unused  G   O   L   -
  54 ////GPIO8          BOARD ID2    G   I   -   -
  55 ////GPIO9   unused  G   O   L   -
  56 ////GPIO10  SMC_EXTSMI# G   I   -   I
  57 ////GPIO11  Nonfunction G   O   H   -
  58 ////GPIO12  unused  G   O   L   -
  59 ////GPIO13  SMC_WAKE_SCI#   G   I   -   I
  60 ////GPIO14  unused  G   O   L   -
  61 ////GPIO15  unused  G   O   L   -
  62 ////GPIO16  PM_DPRSLPVR N   -   -   -
  63 ////GNT5#/GPIO17    GNT5#   N   -   -   -
  64 ////STPPCI#/GPIO18  PM_STPPCI#  N   -   -   -
  65 ////STPCPU#/GPIO20  PM_STPCPU#  N   -   -   -
  66 ////GPIO22  CRT_RefClk  G   I   -   -
  67 ////GPIO23  unused  G   O   L   -
  68 ////GPIO24  unused  G   O   L   -
  69 ////GPIO25  DMI strap   G   O   L   -
  70 ////GPIO26  unused  G   O   L   -
  71 ////GPIO27  unused  G   O   L   -
  72 ////GPIO28  RF_KILL#    G   O   H   -
  73 ////OC5#/GPIO29 OC  N   -   -   -
  74 ////OC6#/GPIO30 OC  N   -   -   -
  75 ////OC7#/GPIO31 OC  N   -   -   -
  76 ////CLKRUN#/GPIO32  PM_CLKRUN#  N   -   -   -
  77 ////GPIO33  NC  G   O   L   -
  78 ////GPIO34  BOARD ID0   G   I   -   -
  79 ////GPIO36  unused  G   O   L   -
  80 ////GPIO38  BOARD ID1   G   I   -   -
  81 ////GPIO39  unused  G   O   L   -
  82 ////GPIO48  unused  G   O   L   -
  83 ////CPUPWRGD/GPIO49 H_PWRGD N   -   -   -
  84 //
  85 //#define   GPIO_USE_SEL_VAL              0x1FC0FFFF       //GPIO1, 10, 13 is EC signal
  86 //#define   GPIO_USE_SEL2_VAL             0x000100D6
  87 //#define   GPIO_IO_SEL_VAL               0x00402502
  88 //#define   GPIO_IO_SEL2_VAL              0x00000044
  89 //#define   GPIO_LVL_VAL                  0x1800083D
  90 //#define   GPIO_LVL2_VAL                 0x00000000
  91 //#define   GPIO_INV_VAL                  0x00002402
  92 //#define   GPIO_BLNK_VAL                 0x00000000
  93 //#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
  94
  95 //
  96 // GPIO Register Settings for CedarRock and CedarFalls platforms
  97 //
  98 //      GPIO Register Settings for NB10_CRB
  99 //---------------------------------------------------------------------------------
 100 //Signal        Used As         USE         I/O     LVL
 101 //---------------------------------------------------------------------------------
 102 //
 103 // GPIO0    FP_AUDIO_DETECT     G       I
 104 // GPIO1    SMC_RUNTIME_SCI#    G       I
 105 // GPIO2        INT_PIRQE_N     N       I
 106 // GPIO3    INT_PIRQF_N     N       I
 107 // GPIO4        INT_PIRQG_N     N       I
 108 // GPIO5        INT_PIRQH_N     N       I
 109 // GPIO6
 110 // GPIO7
 111 // GPIO8
 112 // GPIO9    LPC_SIO_PME     G       I
 113 // GPIO10   SMC_EXTSMI_N        G       I
 114 // GPIO11   SMBALERT- pullup    N
 115 // GPIO12   ICH_GP12        G       I
 116 // GPIO13   SMC_WAKE_SCI_N      G       I
 117 // GPIO14   LCD_PID0        G       O       H
 118 // GPIO15   CONFIG_MODE_N       G       I
 119 // GPIO16       PM_DPRSLPVR     N
 120 // GPIO17   SPI_SELECT_STRAP1
 121 //          /L_BKLTSEL0_N   G       I
 122 // GPIO18   PM_STPPCI_N     N
 123 // GPIO19
 124 // GPIO20   PM_STPCPU_N     N
 125 // GPIO21
 126 // GPIO22   REQ4B           G       I
 127 // GPIO23   L_DRQ1_N        N
 128 // GPIO24   CRB_SV_DET_N        G       O       H
 129 // GPIO25   DMI strap
 130 //          / L_BKLTSEL1_N  G       O       H
 131 // GPIO26   LCD_PID1        G       O       H
 132 // GPIO27   TPEV_DDR3L_DETECT   G       O       H
 133 // GPIO28   RF_KILL         G       O       H:enable
 134 // GPIO29   OC          N
 135 // GPIO30   OC          N
 136 // GPIO31   OC          N
 137 // GPIO32   PM_CLKRUN_N     Native
 138 // GPIO33   MFG_MODE_N      G       I
 139 // GPIO34   BOARD ID0       G       I
 140 // GPIO35
 141 // GPIO36   SV_SET_UP       G       O       H
 142 // GPIO37
 143 // GPIO38   BOARD ID1       G       I
 144 // GPIO39   BOARD ID2       G       I
 145 // GPIO48   FLASH_SEL0      N
 146 // GPIO49   H_PWRGD         N
 147
 148 #define ICH_GPI_ROUTE_SMI(Gpio)          ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))
 149 #define ICH_GPI_ROUTE_SCI(Gpio)          ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))
 150
 151 #define   GPIO_USE_SEL_VAL              0X1F42F7C3
 152 #define   GPIO_USE_SEL2_VAL             0X000000D6
 153 #define   GPIO_IO_SEL_VAL               0X1042B73F
 154 #define   GPIO_IO_SEL2_VAL              0X000100C6
 155 #define   GPIO_LVL_VAL                  0X1F15F601
 156 #define   GPIO_LVL2_VAL                 0X000200D7
 157 #define   GPIO_INV_VAL                  0x00002602
 158 #define   GPIO_BLNK_VAL                 0x00040000
 159 #define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
 160
 161 #endif