3 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #ifndef _FIRMWARE_UPDATE_H_
12 #define _FIRMWARE_UPDATE_H_
18 #include <Guid/FileInfo.h>
20 #include <Protocol/FirmwareVolumeBlock.h>
21 #include <Protocol/LoadedImage.h>
22 #include <Protocol/SimpleFileSystem.h>
23 #include <Protocol/Spi.h>
25 #include <Library/BaseLib.h>
26 #include <Library/BaseMemoryLib.h>
27 #include <Library/CacheMaintenanceLib.h>
28 #include <Library/DebugLib.h>
29 #include <Library/FileHandleLib.h>
30 #include <Library/HiiLib.h>
31 #include <Library/MemoryAllocationLib.h>
32 #include <Library/PcdLib.h>
33 #include <Library/PrintLib.h>
34 #include <Library/ShellLib.h>
35 #include <Library/UefiApplicationEntryPoint.h>
36 #include <Library/UefiBootServicesTableLib.h>
37 #include <Library/UefiLib.h>
38 #include <Library/UefiRuntimeServicesTableLib.h>
41 // Function Prototypes.
48 OUT UINT32
*BufferSize
54 IN EFI_PHYSICAL_ADDRESS BaseAddress
61 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
68 InternalCompareBlock (
69 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
76 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
92 IN OUT UINT32
*NumBytes
,
101 IN OUT UINT32
*NumBytes
,
122 IN EFI_HANDLE ImageHandle
,
123 IN EFI_SYSTEM_TABLE
*SystemTable
127 // Flash specific definitions.
128 // - Should we use a PCD for this information?
130 #define BLOCK_SIZE SIZE_4KB
133 // Flash region layout and update information.
136 EFI_PHYSICAL_ADDRESS Base
;
142 // MAC Address information.
144 #define MAC_ADD_STR_LEN 12
145 #define MAC_ADD_STR_SIZE (MAC_ADD_STR_LEN + 1)
146 #define MAC_ADD_BYTE_COUNT 6
147 #define MAC_ADD_TMP_STR_LEN 2
148 #define MAC_ADD_TMP_STR_SIZE (MAC_ADD_TMP_STR_LEN + 1)
151 // Command Line Data.
153 #define INPUT_STRING_LEN 255
154 #define INPUT_STRING_SIZE (INPUT_STRING_LEN + 1)
156 BOOLEAN UpdateFromFile
;
157 CHAR16 FileName
[INPUT_STRING_SIZE
];
159 UINT8 MacValue
[MAC_ADD_BYTE_COUNT
];
160 BOOLEAN FullFlashUpdate
;
164 // Prefix Opcode Index on the host SPI controller.
167 SPI_WREN
, // Prefix Opcode 0: Write Enable.
168 SPI_EWSR
, // Prefix Opcode 1: Enable Write Status Register.
169 } PREFIX_OPCODE_INDEX
;
172 // Opcode Menu Index on the host SPI controller.
175 SPI_READ_ID
, // Opcode 0: READ ID, Read cycle with address.
176 SPI_READ
, // Opcode 1: READ, Read cycle with address.
177 SPI_RDSR
, // Opcode 2: Read Status Register, No address.
178 SPI_WRDI_SFDP
, // Opcode 3: Write Disable or Discovery Parameters, No address.
179 SPI_SERASE
, // Opcode 4: Sector Erase (4KB), Write cycle with address.
180 SPI_BERASE
, // Opcode 5: Block Erase (32KB), Write cycle with address.
181 SPI_PROG
, // Opcode 6: Byte Program, Write cycle with address.
182 SPI_WRSR
, // Opcode 7: Write Status Register, No address.