Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c

   1 /** @file
   2   This PEIM will parse the hoblist from fsp and report them into pei core.
   3   This file contains the main entrypoint of the PEIM.
   4
   5   Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10
  11 #include <PiPei.h>
  12 #include <Library/IoLib.h>
  13 #include <Library/SerialPortLib.h>
  14
  15 #define PCI_IDX        0xCF8
  16 #define PCI_DAT        0xCFC
  17
  18 #define PCI_LPC_BASE    (0x8000F800)
  19 #define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))
  20
  21 #define PMC_BASE_ADDRESS                  0xFED03000    // PMC Memory Base Address
  22 #define R_PCH_LPC_PMC_BASE                        0x44  // PBASE, 32bit, 512 Bytes
  23 #define B_PCH_LPC_PMC_BASE_EN                     BIT1  // Enable Bit
  24 #define R_PCH_PMC_GEN_PMCON_1                     0x20  // General PM Configuration 1
  25 #define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR           BIT14 // SUS Well Power Failure
  26 #define B_PCH_PMC_GEN_PMCON_PWROK_FLR             BIT16 // PWROK Failure
  27
  28 #define R_PCH_LPC_UART_CTRL                       0x80  // UART Control
  29 #define B_PCH_LPC_UART_CTRL_COM1_EN               BIT0  // COM1 Enable
  30
  31 #define ILB_BASE_ADDRESS                  0xFED08000    // ILB Memory Base Address
  32 #define R_PCH_ILB_IRQE                            0x88  // IRQ Enable Control
  33
  34 #define IO_BASE_ADDRESS                   0xFED0C000    // IO Memory Base Address
  35
  36 #define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3  // UART IRQ3 Enable
  37 #define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4             BIT4  // UART IRQ4 Enable
  38 #define PCIEX_BASE_ADDRESS                        0xE0000000
  39 #define PCI_EXPRESS_BASE_ADDRESS                  PCIEX_BASE_ADDRESS
  40 #define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
  41 #define SB_RCBA                                   0xfed1c000
  42
  43 typedef enum {
  44   PchA0         = 0,
  45   PchA1         = 1,
  46   PchB0         = 2,
  47   PchB1         = 3,
  48   PchB2         = 4,
  49   PchB3         = 5,
  50   PchC0         = 6,
  51   PchSteppingMax
  52 } PCH_STEPPING;
  53
  54 #define MmPciAddress( Segment, Bus, Device, Function, Register ) \
  55   ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
  56     (UINTN)(Bus << 20) + \
  57     (UINTN)(Device << 15) + \
  58     (UINTN)(Function << 12) + \
  59     (UINTN)(Register) \
  60   )
  61
  62 #define DEFAULT_PCI_BUS_NUMBER_PCH  0
  63 #define PCI_DEVICE_NUMBER_PCH_LPC                 31
  64 #define PCI_FUNCTION_NUMBER_PCH_LPC               0
  65
  66 #define R_PCH_LPC_RID_CC                          0x08  // Revision ID & Class Code
  67
  68 #define V_PCH_LPC_RID_0                           0x01  // A0 Stepping (17 x 17)
  69 #define V_PCH_LPC_RID_1                           0x02  // A0 Stepping (25 x 27)
  70 #define V_PCH_LPC_RID_2                           0x03  // A1 Stepping (17 x 17)
  71 #define V_PCH_LPC_RID_3                           0x04  // A1 Stepping (25 x 27)
  72 #define V_PCH_LPC_RID_4                           0x05  // B0 Stepping (17 x 17)
  73 #define V_PCH_LPC_RID_5                           0x06  // B0 Stepping (25 x 27)
  74 #define V_PCH_LPC_RID_6                           0x07  // B1 Stepping (17 x 17)
  75 #define V_PCH_LPC_RID_7                           0x08  // B1 Stepping (25 x 27)
  76 #define V_PCH_LPC_RID_8                           0x09  // B2 Stepping (17 x 17)
  77 #define V_PCH_LPC_RID_9                           0x0A  // B2 Stepping (25 x 27)
  78 #define V_PCH_LPC_RID_A                           0x0B  // B3 Stepping (17 x 17)
  79 #define V_PCH_LPC_RID_B                           0x0C  // B3 Stepping (25 x 27)
  80 #define V_PCH_LPC_RID_C                           0x0D  // C0 Stepping (17 x 17)
  81 #define V_PCH_LPC_RID_D                           0x0E  // C0 Stepping (25 x 27)
  82
  83 /**
  84   Return Pch stepping type
  85
  86   @param[in] None
  87
  88   @retval PCH_STEPPING            Pch stepping type
  89
  90 **/
  91 PCH_STEPPING
  92 EFIAPI
  93 PchStepping (
  94   VOID
  95   )
  96 {
  97   UINT8 RevId;
  98
  99   RevId = MmioRead8 (
 100           MmPciAddress (0,
 101             DEFAULT_PCI_BUS_NUMBER_PCH,
 102             PCI_DEVICE_NUMBER_PCH_LPC,
 103             PCI_FUNCTION_NUMBER_PCH_LPC,
 104             R_PCH_LPC_RID_CC)
 105           );
 106
 107   switch (RevId) {
 108     case V_PCH_LPC_RID_0:
 109     case V_PCH_LPC_RID_1:
 110       return PchA0;
 111       break;
 112
 113     case V_PCH_LPC_RID_2:
 114     case V_PCH_LPC_RID_3:
 115       return PchA1;
 116       break;
 117
 118     case V_PCH_LPC_RID_4:
 119     case V_PCH_LPC_RID_5:
 120       return PchB0;
 121       break;
 122
 123     case V_PCH_LPC_RID_6:
 124     case V_PCH_LPC_RID_7:
 125       return PchB1;
 126       break;
 127
 128     case V_PCH_LPC_RID_8:
 129     case V_PCH_LPC_RID_9:
 130       return PchB2;
 131       break;
 132
 133     case V_PCH_LPC_RID_A:
 134     case V_PCH_LPC_RID_B:
 135       return PchB3;
 136       break;
 137
 138     case V_PCH_LPC_RID_C:
 139     case V_PCH_LPC_RID_D:
 140       return PchC0;
 141       break;
 142
 143     default:
 144       return PchSteppingMax;
 145       break;
 146
 147   }
 148 }
 149
 150 /**
 151   Enable legacy decoding on ICH6
 152
 153  @param[in] none
 154
 155  @retval EFI_SUCCESS     Always returns success.
 156
 157 **/
 158 VOID
 159 EnableInternalUart(
 160   VOID
 161   )
 162 {
 163
 164   //
 165   // Program and enable PMC Base.
 166   //
 167   IoWrite32 (PCI_IDX,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
 168   IoWrite32 (PCI_DAT,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
 169
 170   //
 171   // Enable COM1 for debug message output.
 172   //
 173   MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
 174
 175   //
 176   // Silicon Steppings
 177   //
 178   if (PchStepping()>= PchB0)
 179     MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);
 180   else
 181     MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
 182   MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
 183   MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
 184   MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
 185   MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
 186   MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);
 187
 188   SerialPortInitialize ();
 189   SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);
 190
 191   return  ;
 192 }