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1 /*++
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13
14
15 Module Name:
16
17 CpuIA32.h
18
19 Abstract:
20
21 --*/
22
23 #ifndef _CPU_IA32_H
24 #define _CPU_IA32_H
25
26 typedef struct {
27 UINT32 RegEax;
28 UINT32 RegEbx;
29 UINT32 RegEcx;
30 UINT32 RegEdx;
31 } EFI_CPUID_REGISTER;
32
33 typedef struct {
34 UINT32 HeaderVersion;
35 UINT32 UpdateRevision;
36 UINT32 Date;
37 UINT32 ProcessorId;
38 UINT32 Checksum;
39 UINT32 LoaderRevision;
40 UINT32 ProcessorFlags;
41 UINT32 DataSize;
42 UINT32 TotalSize;
43 UINT8 Reserved[12];
44 } EFI_CPU_MICROCODE_HEADER;
45
46 typedef struct {
47 UINT32 ExtendedSignatureCount;
48 UINT32 ExtendedTableChecksum;
49 UINT8 Reserved[12];
50 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
51
52 typedef struct {
53 UINT32 ProcessorSignature;
54 UINT32 ProcessorFlag;
55 UINT32 ProcessorChecksum;
56 } EFI_CPU_MICROCODE_EXTENDED_TABLE;
57
58 typedef struct {
59 UINT32 Stepping : 4;
60 UINT32 Model : 4;
61 UINT32 Family : 4;
62 UINT32 Type : 2;
63 UINT32 Reserved1 : 2;
64 UINT32 ExtendedModel : 4;
65 UINT32 ExtendedFamily : 8;
66 UINT32 Reserved2 : 4;
67 } EFI_CPU_VERSION;
68
69 #define EFI_CPUID_SIGNATURE 0x0
70 #define EFI_CPUID_VERSION_INFO 0x1
71 #define EFI_CPUID_CACHE_INFO 0x2
72 #define EFI_CPUID_SERIAL_NUMBER 0x3
73 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
74 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
75 #define EFI_CPUID_BRAND_STRING1 0x80000002
76 #define EFI_CPUID_BRAND_STRING2 0x80000003
77 #define EFI_CPUID_BRAND_STRING3 0x80000004
78
79 #define EFI_MSR_IA32_PLATFORM_ID 0x17
80 #define EFI_MSR_IA32_APIC_BASE 0x1B
81 #define EFI_MSR_EBC_HARD_POWERON 0x2A
82 #define EFI_MSR_EBC_SOFT_POWERON 0x2B
83 #define BINIT_DRIVER_DISABLE 0x40
84 #define INTERNAL_MCERR_DISABLE 0x20
85 #define INITIATOR_MCERR_DISABLE 0x10
86 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C
87 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
88 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
89 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD
90 #define EFI_APIC_GLOBAL_ENABLE 0x800
91 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0
92 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
93 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
94 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
95 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
96 #define FAST_STRING_ENABLE_BIT 0x00000001
97
98 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
99 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F
100 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
101 #define EFI_CACHE_MTRR_VALID 0x800
102 #define EFI_CACHE_FIXED_MTRR_VALID 0x400
103 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
104 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
105 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
106 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
107
108 #define EFI_IA32_MTRR_FIX64K_00000 0x250
109 #define EFI_IA32_MTRR_FIX16K_80000 0x258
110 #define EFI_IA32_MTRR_FIX16K_A0000 0x259
111 #define EFI_IA32_MTRR_FIX4K_C0000 0x268
112 #define EFI_IA32_MTRR_FIX4K_C8000 0x269
113 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A
114 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B
115 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C
116 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D
117 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E
118 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F
119
120 #define EFI_IA32_MCG_CAP 0x179
121 #define EFI_IA32_MCG_CTL 0x17B
122 #define EFI_IA32_MC0_CTL 0x400
123 #define EFI_IA32_MC0_STATUS 0x401
124
125 #define EFI_IA32_PERF_STATUS 0x198
126 #define EFI_IA32_PERF_CTL 0x199
127
128 #define EFI_CACHE_UNCACHEABLE 0
129 #define EFI_CACHE_WRITECOMBINING 1
130 #define EFI_CACHE_WRITETHROUGH 4
131 #define EFI_CACHE_WRITEPROTECTED 5
132 #define EFI_CACHE_WRITEBACK 6
133
134 //
135 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
136 //
137 #define EfiMakeCpuVersion(f, m, s) \
138 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
139
140 /**
141 Halt the Cpu
142
143 @param[in] None
144
145 @retval None
146
147 **/
148 VOID
149 EFIAPI
150 EfiHalt (
151 VOID
152 );
153
154 /**
155 Write back and invalidate the Cpu cache
156
157 @param[in] None
158
159 @retval None
160
161 **/
162 VOID
163 EFIAPI
164 EfiWbinvd (
165 VOID
166 );
167
168 /**
169 Invalidate the Cpu cache
170
171 @param[in] None
172
173 @retval None
174
175 **/
176 VOID
177 EFIAPI
178 EfiInvd (
179 VOID
180 );
181
182 /**
183 Get the Cpu info by execute the CPUID instruction
184
185 @param[in] RegisterInEax The input value to put into register EAX
186 @param[in] Regs The Output value
187
188 @retval None
189
190 **/
191 VOID
192 EFIAPI
193 EfiCpuid (
194 IN UINT32 RegisterInEax,
195 OUT EFI_CPUID_REGISTER *Regs
196 );
197
198 /**
199 When RegisterInEax != 4, the functionality is the same as EfiCpuid.
200 When RegisterInEax == 4, the function return the deterministic cache
201 parameters by excuting the CPUID instruction.
202
203 @param[in] RegisterInEax The input value to put into register EAX.
204 @param[in] CacheLevel The deterministic cache level.
205 @param[in] Regs The Output value.
206
207 @retval None
208
209 **/
210 VOID
211 EFIAPI
212 EfiCpuidExt (
213 IN UINT32 RegisterInEax,
214 IN UINT32 CacheLevel,
215 OUT EFI_CPUID_REGISTER *Regs
216 );
217
218 /**
219 Read Cpu MSR
220
221 @param[in] Index The index value to select the register
222
223 @retval Return the read data
224
225 **/
226 UINT64
227 EFIAPI
228 EfiReadMsr (
229 IN UINT32 Index
230 );
231
232 /**
233 Write Cpu MSR
234
235 @param[in] Index The index value to select the register
236 @param[in] Value The value to write to the selected register
237
238 @retval None
239
240 **/
241 VOID
242 EFIAPI
243 EfiWriteMsr (
244 IN UINT32 Index,
245 IN UINT64 Value
246 );
247
248 /**
249 Read Time stamp
250
251 @param[in] None
252
253 @retval Return the read data
254
255 **/
256 UINT64
257 EFIAPI
258 EfiReadTsc (
259 VOID
260 );
261
262 /**
263 Writing back and invalidate the cache,then diable it
264
265 @param[in] None
266
267 @retval None
268
269 **/
270 VOID
271 EFIAPI
272 EfiDisableCache (
273 VOID
274 );
275
276 /**
277 Invalidate the cache,then Enable it
278
279 @param[in] None
280
281 @retval None
282
283 **/
284 VOID
285 EFIAPI
286 EfiEnableCache (
287 VOID
288 );
289
290 /**
291 Get Eflags
292
293 @param[in] None
294
295 @retval Return the Eflags value
296
297 **/
298 UINT32
299 EFIAPI
300 EfiGetEflags (
301 VOID
302 );
303
304 /**
305 Disable Interrupts
306
307 @param[in] None
308
309 @retval None
310
311 **/
312 VOID
313 EFIAPI
314 EfiDisableInterrupts (
315 VOID
316 );
317
318 /**
319 Enable Interrupts
320
321 @param[in] None
322
323 @retval None
324
325 **/
326 VOID
327 EFIAPI
328 EfiEnableInterrupts (
329 VOID
330 );
331
332 /**
333 Extract CPU detail version infomation
334
335 @param[in] FamilyId FamilyId, including ExtendedFamilyId
336 @param[in] Model Model, including ExtendedModel
337 @param[in] SteppingId SteppingId
338 @param[in] Processor Processor
339
340 **/
341 VOID
342 EFIAPI
343 EfiCpuVersion (
344 IN UINT16 *FamilyId, OPTIONAL
345 IN UINT8 *Model, OPTIONAL
346 IN UINT8 *SteppingId, OPTIONAL
347 IN UINT8 *Processor OPTIONAL
348 );
349
350 #endif