3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
35 UINT32 UpdateRevision
;
39 UINT32 LoaderRevision
;
40 UINT32 ProcessorFlags
;
44 } EFI_CPU_MICROCODE_HEADER
;
47 UINT32 ExtendedSignatureCount
;
48 UINT32 ExtendedTableChecksum
;
50 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
;
53 UINT32 ProcessorSignature
;
55 UINT32 ProcessorChecksum
;
56 } EFI_CPU_MICROCODE_EXTENDED_TABLE
;
64 UINT32 ExtendedModel
: 4;
65 UINT32 ExtendedFamily
: 8;
69 #define EFI_CPUID_SIGNATURE 0x0
70 #define EFI_CPUID_VERSION_INFO 0x1
71 #define EFI_CPUID_CACHE_INFO 0x2
72 #define EFI_CPUID_SERIAL_NUMBER 0x3
73 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
74 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
75 #define EFI_CPUID_BRAND_STRING1 0x80000002
76 #define EFI_CPUID_BRAND_STRING2 0x80000003
77 #define EFI_CPUID_BRAND_STRING3 0x80000004
79 #define EFI_MSR_IA32_PLATFORM_ID 0x17
80 #define EFI_MSR_IA32_APIC_BASE 0x1B
81 #define EFI_MSR_EBC_HARD_POWERON 0x2A
82 #define EFI_MSR_EBC_SOFT_POWERON 0x2B
83 #define BINIT_DRIVER_DISABLE 0x40
84 #define INTERNAL_MCERR_DISABLE 0x20
85 #define INITIATOR_MCERR_DISABLE 0x10
86 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C
87 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
88 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
89 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD
90 #define EFI_APIC_GLOBAL_ENABLE 0x800
91 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0
92 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
93 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
94 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
95 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
96 #define FAST_STRING_ENABLE_BIT 0x00000001
98 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
99 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F
100 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
101 #define EFI_CACHE_MTRR_VALID 0x800
102 #define EFI_CACHE_FIXED_MTRR_VALID 0x400
103 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
104 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
105 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
106 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
108 #define EFI_IA32_MTRR_FIX64K_00000 0x250
109 #define EFI_IA32_MTRR_FIX16K_80000 0x258
110 #define EFI_IA32_MTRR_FIX16K_A0000 0x259
111 #define EFI_IA32_MTRR_FIX4K_C0000 0x268
112 #define EFI_IA32_MTRR_FIX4K_C8000 0x269
113 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A
114 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B
115 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C
116 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D
117 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E
118 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F
120 #define EFI_IA32_MCG_CAP 0x179
121 #define EFI_IA32_MCG_CTL 0x17B
122 #define EFI_IA32_MC0_CTL 0x400
123 #define EFI_IA32_MC0_STATUS 0x401
125 #define EFI_IA32_PERF_STATUS 0x198
126 #define EFI_IA32_PERF_CTL 0x199
128 #define EFI_CACHE_UNCACHEABLE 0
129 #define EFI_CACHE_WRITECOMBINING 1
130 #define EFI_CACHE_WRITETHROUGH 4
131 #define EFI_CACHE_WRITEPROTECTED 5
132 #define EFI_CACHE_WRITEBACK 6
135 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
137 #define EfiMakeCpuVersion(f, m, s) \
138 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
155 Write back and invalidate the Cpu cache
169 Invalidate the Cpu cache
183 Get the Cpu info by execute the CPUID instruction
185 @param[in] RegisterInEax The input value to put into register EAX
186 @param[in] Regs The Output value
194 IN UINT32 RegisterInEax
,
195 OUT EFI_CPUID_REGISTER
*Regs
199 When RegisterInEax != 4, the functionality is the same as EfiCpuid.
200 When RegisterInEax == 4, the function return the deterministic cache
201 parameters by excuting the CPUID instruction.
203 @param[in] RegisterInEax The input value to put into register EAX.
204 @param[in] CacheLevel The deterministic cache level.
205 @param[in] Regs The Output value.
213 IN UINT32 RegisterInEax
,
214 IN UINT32 CacheLevel
,
215 OUT EFI_CPUID_REGISTER
*Regs
221 @param[in] Index The index value to select the register
223 @retval Return the read data
235 @param[in] Index The index value to select the register
236 @param[in] Value The value to write to the selected register
253 @retval Return the read data
263 Writing back and invalidate the cache,then diable it
277 Invalidate the cache,then Enable it
295 @retval Return the Eflags value
314 EfiDisableInterrupts (
328 EfiEnableInterrupts (
333 Extract CPU detail version infomation
335 @param[in] FamilyId FamilyId, including ExtendedFamilyId
336 @param[in] Model Model, including ExtendedModel
337 @param[in] SteppingId SteppingId
338 @param[in] Processor Processor
344 IN UINT16
*FamilyId
, OPTIONAL
345 IN UINT8
*Model
, OPTIONAL
346 IN UINT8
*SteppingId
, OPTIONAL
347 IN UINT8
*Processor OPTIONAL