Vlv2TbltDevicePkg/Include/Platform.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9
  10 Module Name:
  11
  12   Platform.h
  13
  14 Abstract:
  15
  16   Pinetrail platform specific information.
  17
  18 **/
  19
  20 #ifndef _PLATFORM_H
  21 #define _PLATFORM_H
  22
  23 #include "ChipsetAccess.h"
  24 #include "PlatformBaseAddresses.h"
  25
  26
  27 //
  28 // Number of P & T states supported.
  29 //
  30 #define NPTM_P_STATES_SUPPORTED         16
  31 #define NPTM_T_STATES_SUPPORTED         8
  32
  33 //
  34 // I/O APIC IDs, the code uses math to generate the numbers
  35 // instead of using these defines.
  36 //
  37 #define ICH_IOAPIC                     (1 << 0)
  38 #define ICH_IOAPIC_ID                   0x08
  39
  40 //
  41 // Possible SMBus addresses that will be present.
  42 //
  43 #define SMBUS_ADDR_CH_A_1     0xA0
  44 #define SMBUS_ADDR_CH_A_2     0xA2
  45 #define SMBUS_ADDR_CH_B_1     0xA4
  46 #define SMBUS_ADDR_CH_B_2     0xA6
  47 #define SMBUS_ADDR_CH_C_1     0xA8
  48 #define SMBUS_ADDR_CH_C_2     0xAA
  49 #define SMBUS_ADDR_CH_D_1     0xAC
  50 #define SMBUS_ADDR_CH_D_2     0xAE
  51 #define SMBUS_ADDR_HOST_CLK_BUFFER  0xDC
  52 #define SMBUS_ADDR_ICH_SLAVE        0x44
  53 #define SMBUS_ADDR_HECETA     0x5C
  54 #define SMBUS_ADDR_SMBARP     0xC2
  55 #define SMBUS_ADDR_82573E     0xC6
  56 #define SMBUS_ADDR_CLKCHIP    0xD2
  57 #define SMBUS_ADDR_BRD_REV          0x4E
  58 #define SMBUS_ADDR_DB803            0x82
  59
  60 //
  61 // SMBus addresses that used on this platform.
  62 //
  63 #define PLATFORM_SMBUS_RSVD_ADDRESSES { \
  64   SMBUS_ADDR_CH_A_1, \
  65   SMBUS_ADDR_CH_A_2, \
  66   SMBUS_ADDR_HOST_CLK_BUFFER, \
  67   SMBUS_ADDR_ICH_SLAVE, \
  68   SMBUS_ADDR_SMBARP, \
  69   SMBUS_ADDR_CLKCHIP, \
  70   SMBUS_ADDR_BRD_REV, \
  71   SMBUS_ADDR_DB803 \
  72   }
  73
  74 //
  75 // Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
  76 //
  77 #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
  78
  79 //
  80 // CMOS usage
  81 //
  82 #define CMOS_CPU_BSP_SELECT         0x10
  83 #define CMOS_CPU_UP_MODE            0x11
  84 #define CMOS_CPU_RATIO_OFFSET       0x12
  85 #define CMOS_CPU_CORE_HT_OFFSET     0x13
  86 #define CMOS_EFI_DEBUG              0x14
  87 #define CMOS_CPU_BIST_OFFSET        0x15
  88 #define CMOS_CPU_VMX_OFFSET         0x16
  89 #define CMOS_ICH_PORT80_OFFSET      0x17
  90 #define CMOS_PLATFORM_DESIGNATOR    0x18      // Second bank CMOS location of Platform ID.
  91 #define CMOS_VALIDATION_TEST_BYTE   0x19      // BIT0 - Validation mailbox for UPonDP.
  92 #define CMOS_SERIAL_BAUD_RATE       0x1A      // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
  93 #define CMOS_DCU_MODE_OFFSET        0x1B
  94 #define CMOS_VR11_SET_OFFSET        0x1C
  95 #define CMOS_SBSP_TO_AP_COMM        0x20      // SEC code use ONLY!!!
  96 #define CMOS_RESET_TYPE_BY_OS       0x52
  97 #define TCG_CMOS_MOR_AREA_OFFSET    0x65      // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
  98 #define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
  99 #define ACPI_TPM_REQUEST            0x75
 100 #define ACPI_TPM_LAST_REQUEST       0x76
 101 #define CMOS_BOOT_FLAG_ADDRESS      0x7E
 102
 103 //
 104 // GPIO Index Data Structure.
 105 //
 106 typedef struct {
 107   UINT8   Register;
 108   UINT32  Value;
 109 } ICH_GPIO_DEV;
 110
 111 //
 112 // CPU Equates
 113 //
 114 #define MAX_THREAD                      2
 115 #define MAX_CORE                        1
 116 #define MAX_DIE                         2
 117 #define MAX_CPU_SOCKET                  1
 118 #define MAX_CPU_NUM                     (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)
 119
 120 #define MEM64_LEN                       0x00100000000
 121 #define RES_MEM64_36_BASE               0x01000000000 - MEM64_LEN   // 2^36
 122 #define RES_MEM64_36_LIMIT              0x01000000000 - 1           // 2^36
 123 #define RES_MEM64_39_BASE               0x08000000000 - MEM64_LEN   // 2^39
 124 #define RES_MEM64_39_LIMIT              0x08000000000 - 1           // 2^39
 125 #define RES_MEM64_40_BASE               0x10000000000 - MEM64_LEN   // 2^40
 126 #define RES_MEM64_40_LIMIT              0x10000000000 - 1           // 2^40
 127
 128 #define PLATFORM_MAX_BUS_NUM             0x3f
 129 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID    0x574d
 130 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b
 131 #define V_DEFAULT_SUBSYSTEM_VENDOR_ID    0x8086
 132
 133 #endif