Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h

   1 /** @file
   2
   3   Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.<BR>
   4
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9
  10
  11
  12 Module Name:
  13
  14   GlobalNvsArea.h
  15
  16 Abstract:
  17
  18   Definition of the global NVS area protocol.  This protocol
  19   publishes the address and format of a global ACPI NVS buffer used as a communications
  20   buffer between SMM code and ASL code.
  21   The format is derived from the ACPI reference code, version 0.95.
  22
  23   Note:  Data structures defined in this protocol are not naturally aligned.
  24
  25 **/
  26
  27
  28 #ifndef _GLOBAL_NVS_AREA_H_
  29 #define _GLOBAL_NVS_AREA_H_
  30
  31 //
  32 // Includes
  33 //
  34 #define GLOBAL_NVS_DEVICE_ENABLE 1
  35 #define GLOBAL_NVS_DEVICE_DISABLE 0
  36
  37 //
  38 // Forward reference for pure ANSI compatibility
  39 //
  40
  41 //EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);
  42
  43 //
  44 // Global NVS Area Protocol GUID
  45 //
  46 #define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
  47 { 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
  48
  49 //
  50 // Revision id - Added TPM related fields
  51 //
  52 #define GLOBAL_NVS_AREA_RIVISION_1       1
  53
  54 //
  55 // Extern the GUID for protocol users.
  56 //
  57 extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
  58
  59 //
  60 // Global NVS Area definition
  61 //
  62 #pragma pack (1)
  63 typedef struct {
  64   //
  65   // Miscellaneous Dynamic Values, the definitions below need to be matched
  66   // GNVS definitions in Platform.ASL
  67   //
  68   UINT16      OperatingSystem;    // 00
  69   UINT8       SmiFunction;        // 02   SMI function call via IO Trap
  70   UINT8       SmiParameter0;      // 03
  71   UINT8       SmiParameter1;      // 04
  72   UINT8       SciFunction;        // 05   SCI function call via _L00
  73   UINT8       SciParameter0;      // 06
  74   UINT8       SciParameter1;      // 07
  75   UINT8       GlobalLock;         // 08   Global lock function call
  76   UINT8       LockParameter0;     // 09
  77   UINT8       LockParameter1;     // 10
  78   UINT32      Port80DebugValue;   // 11
  79   UINT8       LidState;           // 15   Open = 1
  80   UINT8       PowerState;         // 16   AC = 1
  81   UINT8       DebugState;         // 17
  82
  83
  84   //
  85   // Thermal Policy Values
  86   //
  87   UINT8       EnableThermalOffset;                        // 18 ThermalOffset for KSC
  88   UINT8       Reserved1;                           // 19
  89   UINT8       Reserved2;                           // 20
  90   UINT8       PassiveThermalTripPoint;                    // 21
  91   UINT8       PassiveTc1Value;                            // 22
  92   UINT8       PassiveTc2Value;                            // 23
  93   UINT8       PassiveTspValue;                            // 24
  94   UINT8       CriticalThermalTripPoint;                   // 25
  95   UINT8       EnableDigitalThermalSensor;                 // 26
  96   UINT8       BspDigitalThermalSensorTemperature;         // 27   Temperature of BSP
  97   UINT8       ApDigitalThermalSensorTemperature;          // 28   Temperature of AP
  98   UINT8       DigitalThermalSensorSmiFunction;            // 29   SMI function call via DTS IO Trap
  99
 100   //
 101   // Battery Support Values
 102   //
 103   UINT8       NumberOfBatteries;      // 30
 104   UINT8       BatteryCapacity0;       // 31   Battery 0 Stored Capacity
 105   UINT8       BatteryCapacity1;       // 32   Battery 1 Stored Capacity
 106   UINT8       BatteryCapacity2;       // 33   Battery 2 Stored Capacity
 107   UINT8       BatteryStatus0;         // 34   Battery 0 Stored Status
 108   UINT8       BatteryStatus1;         // 35   Battery 1 Stored Status
 109   UINT8       BatteryStatus2;         // 36   Battery 2 Stored Status
 110
 111   // NOTE: Do NOT Change the Offset of Revision Field
 112   UINT8       Revision;               // 37   Revision of the structure EFI_GLOBAL_NVS_AREA
 113   UINT8       Reserved3[2];           // 38:39
 114
 115   //
 116   // Processor Configuration Values
 117   //
 118   UINT8       ApicEnable;             // 40   APIC Enabled by SBIOS (APIC Enabled = 1)
 119   UINT8       LogicalProcessorCount;  // 41   Processor Count Enabled (MP Enabled != 0)
 120   UINT8       CurentPdcState0;        // 42   PDC settings, Processor 0
 121   UINT8       CurentPdcState1;        // 43   PDC settings, Processor 1
 122   UINT8       MaximumPpcState;        // 44   Maximum PPC state
 123   UINT32      PpmFlags;               // 45:48 PPM configuration flags, same as CFGD
 124   UINT8       Reserved4[1];           // 49
 125
 126   //
 127   // SIO Configuration Values
 128   //
 129   UINT8       DockedSioPresent;       // 50   Dock SIO Present
 130   UINT8       DockComA;               // 51     COM A Port
 131   UINT8       DockComB;               // 52     COM B Port
 132   UINT8       LptP;                   // 53     LPT Port
 133   UINT8       DockFdc;                // 54     FDC Port
 134   UINT8       OnboardCom;             // 55   Onboard COM Port
 135   UINT8       OnboardComCir;          // 56   Onboard COM CIR Port
 136
 137   UINT8       WPCN381U;               // 57
 138   UINT8       NPCE791x;               // 58
 139   UINT8       Reserved5[1];           // 59
 140
 141   //
 142   // Internal Graphics Device Values
 143   //
 144   UINT8       IgdState;               // 60   IGD State (Primary Display = 1)
 145   UINT8       DisplayToggleList;      // 61   Display Toggle List Selection
 146   UINT8       CurrentDeviceList;      // 62   Current Attached Device List
 147   UINT8       PreviousDeviceList;     // 63   Previous Attached Device List
 148   UINT16      CurrentDisplayState;    // 64   Current Display State
 149   UINT16      NextDisplayState;       // 66   Next Display State
 150   UINT16      SetDisplayState;        // 68   Set Display State
 151   UINT8       NumberOfValidDeviceId;  // 70   Number of Valid Device IDs
 152   UINT32      DeviceId1;              // 71   Device ID 1
 153   UINT32      DeviceId2;              // 75   Device ID 2
 154   UINT32      DeviceId3;              // 79   Device ID 3
 155   UINT32      DeviceId4;              // 83   Device ID 4
 156   UINT32      DeviceId5;              // 87   Device ID 5
 157
 158   UINT32      AKsv0;                  // 91:94 First four bytes of AKSV (manufacturing mode)
 159   UINT8       AKsv1;                  // 95    Fifth byte of AKSV (manufacturing mode
 160
 161   UINT8       Reserved6[7];           // 96:102
 162
 163   //
 164   // Backlight Control Values
 165   //
 166   UINT8       BacklightControlSupport;  // 103  Backlight Control Support
 167   UINT8       BrightnessPercentage;     // 104  Brightness Level Percentage
 168
 169   //
 170   // Ambient Light Sensor Values
 171   //
 172   UINT8       AlsEnable;              // 105  Ambient Light Sensor Enable
 173   UINT8       AlsAdjustmentFactor;    // 106  Ambient Light Adjusment Factor
 174   UINT8       LuxLowValue;            // 107  LUX Low Value
 175   UINT8       LuxHighValue;           // 108  LUX High Value
 176
 177   UINT8       Reserved7[1];           // 109
 178
 179   //
 180   // Extended Mobile Access Values
 181   //
 182   UINT8       EmaEnable;              // 110  EMA Enable
 183   UINT16      EmaPointer;             // 111  EMA Pointer
 184   UINT16      EmaLength;              // 113  EMA Length
 185
 186   UINT8       Reserved8[1];           // 115
 187
 188   //
 189   // Mobile East Fork Values
 190   //
 191   UINT8       MefEnable;              // 116 Mobile East Fork Enable
 192
 193   //
 194   // PCIe Dock Status
 195   //
 196   UINT8       PcieDockStatus;         // 117 PCIe Dock Status
 197
 198   UINT8       Reserved9[2];           // 118:119
 199
 200   //
 201   // TPM Registers
 202   //
 203   UINT8       TpmPresent;             // 120 TPM Present
 204   UINT8       TpmEnable;              // 121 TPM Enable
 205
 206   UINT8       MorData;                // 122 Memory Overwrite Request Data
 207   UINT8       TcgParamter;            // 123 Used for save the Mor and/or physical presence parameter
 208   UINT32      PPResponse;             // 124 Physical Presence request operation response
 209   UINT8       PPRequest;              // 128 Physical Presence request operation
 210   UINT8       LastPPRequest;          // 129 Last Physical Presence request operation
 211
 212   //
 213   // SATA Values
 214   //
 215   UINT8       GtfTaskFileBufferPort0[7];    // 130  GTF Task File Buffer for Port 0
 216   UINT8       GtfTaskFileBufferPort2[7];    // 137  GTF Task File Buffer for Port 2
 217   UINT8       IdeMode;                      // 144  IDE Mode (Compatible\Enhanced)
 218   UINT8       GtfTaskFileBufferPort1[7];    // 145:151 GTF Task File Buffer for Port 1
 219
 220   UINT8       Reserved111[10];                // 152:161
 221   UINT64      BootTimeLogAddress;           // 162:169 Boot Time Log Table Address
 222
 223   UINT32      IgdOpRegionAddress;           // 170  IGD OpRegion Starting Address
 224   UINT8       IgdBootType;                  // 174  IGD Boot Type CMOS option
 225   UINT8       IgdPanelType;                 // 175  IGD Panel Type CMOs option
 226   UINT8       IgdTvFormat;                  // 176  IGD TV Format CMOS option
 227   UINT8       IgdTvMinor;                   // 177  IGD TV Minor Format CMOS option
 228   UINT8       IgdPanelScaling;              // 178  IGD Panel Scaling
 229   UINT8       IgdBlcConfig;                 // 179  IGD BLC Configuration
 230   UINT8       IgdBiaConfig;                 // 180  IGD BIA Configuration
 231   UINT8       IgdSscConfig;                 // 181  IGD SSC Configuration
 232   UINT8       Igd409;                       // 182  IGD 0409 Modified Settings Flag
 233   UINT8       Igd509;                       // 183  IGD 0509 Modified Settings Flag
 234   UINT8       Igd609;                       // 184  IGD 0609 Modified Settings Flag
 235   UINT8       Igd709;                       // 185  IGD 0709 Modified Settings Flag
 236   UINT8       IgdPowerConservation;         // 186  IGD Power Conservation Feature Flag
 237   UINT8       IgdDvmtMemSize;               // 187  IGD DVMT Memory Size
 238   UINT8       IgdFunc1Enable;               // 188  IGD Function 1 Enable
 239   UINT8       IgdHpllVco;                   // 189  HPLL VCO
 240   UINT32      NextStateDid1;                // 190  Next state DID1 for _DGS
 241   UINT32      NextStateDid2;                // 194  Next state DID2 for _DGS
 242   UINT32      NextStateDid3;                // 198  Next state DID3 for _DGS
 243   UINT32      NextStateDid4;                // 202  Next state DID4 for _DGS
 244   UINT32      NextStateDid5;                // 206  Next state DID5 for _DGS
 245   UINT32      NextStateDid6;                // 210  Next state DID6 for _DGS
 246   UINT32      NextStateDid7;                // 214  Next state DID7 for _DGS
 247   UINT32      NextStateDid8;                // 218  Next state DID8 for _DGS
 248   UINT8       IgdSciSmiMode;                // 222  GMCH SMI/SCI mode (0=SCI)
 249   UINT8       IgdPAVP;                      // 223  IGD PAVP data
 250   UINT8       IgdSelfRefresh;               // 224  IGD Self Refresh
 251   UINT8       PcieOSCControl;               // 225  PCIE OSC Control
 252   UINT8       NativePCIESupport;            // 226  Native PCI Express Support
 253
 254   //
 255   // USB Sideband Deferring Support
 256   //
 257   UINT8       HostAlertVector;              // 227  GPE vector used for HOST_ALERT
 258   UINT8       HostAlertPio;                 // 228  PIO of USB device used for HOST_ALERT
 259
 260   UINT8       Reserved112[27];               // 229
 261   UINT32      NvIgOpRegionAddress;          // 256 NVIG support
 262   UINT32      NvHmOpRegionAddress;          // 260 NVHM support
 263   UINT32      ApXmOpRegionAddress;          // 264 AMDA support
 264   UINT32      DeviceId6;                    // 268   Device ID 6
 265   UINT32      DeviceId7;                    // 272   Device ID 7
 266   UINT32      DeviceId8;                    // 276   Device ID 8
 267   UINT32      EndpointBaseAddress;          // 280 PEG Endpoint PCIe Base Address
 268   UINT32      CapStrPresence;               // 284 PEG Endpoint Capability Structure Presence
 269   UINT32      EndpointPcieCapBaseAddress;   // 288 PEG Endpoint PCIe Capability Structure Base Address
 270   UINT32      EndpointVcCapBaseAddress;     // 292 PEG Endpoint Virtual Channel Capability Structure Base Address
 271   UINT32      XPcieCfgBaseAddress;          // 296 Any Device's PCIe Config Space Base Address
 272   UINT32      OccupiedBuses1;               // 300 Occupied Buses from 0 to 31
 273   UINT32      OccupiedBuses2;               // 304 Occupied Buses from 32 to 63
 274   UINT32      OccupiedBuses3;               // 308 Occupied Buses from 64 to 95
 275   UINT32      OccupiedBuses4;               // 312 Occupied Buses from 96 to 127
 276   UINT32      OccupiedBuses5;               // 316 Occupied Buses from 128 to 159
 277   UINT32      OccupiedBuses6;               // 320 Occupied Buses from 160 to 191
 278   UINT32      OccupiedBuses7;               // 324 Occupied Buses from 192 to 223
 279   UINT32      OccupiedBuses8;               // 328 Occupied Buses from 224 to 255
 280   UINT8       UartSelection;                // 332 UART Interface Selection 0: Internal; 1: SIO
 281   UINT8       PcuUart1Enable;               // 333 PCU UART 1 Enabled
 282   UINT8       PcuUart2Enable;               // 334 PCU UART 2 Enabled
 283
 284   UINT32      LPEBar0;                      // 335~338  LPE Bar0
 285   UINT32      LPEBar1;                      // 339~342  LPE Bar1
 286
 287   UINT32      LPEBar2;                      // 343~346  LPE Bar2
 288   UINT8        AcSetup;                      // 347 For Ac Powered Config option - IST applet
 289   UINT8       BatterySetup;                 // 348 For Battery Powered Config option - IST applet
 290   UINT8       PlatformFlavor;               // 349 0:unknown 1: Mobile; 2: desktop
 291   UINT8       Reserved113[1];                // 350
 292
 293   UINT8       IsctReserve;                      // 351 ISCT / AOAC Configuration
 294   UINT8       XhciMode;                     // 352 xHCI mode
 295   UINT8       PmicEnable;                   // 353 PMIC enable
 296
 297   UINT8       LpeEnable;                    // 354 LPE enable
 298   UINT32      ISPAddr;                      // 355 ISP Base address
 299   UINT8       ISPDevSel;                    // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
 300
 301   //
 302   // Lpss controllers
 303   //
 304   UINT32      PCIBottomAddress;            //360  ((4+8+6)*4+2)*4=296
 305   UINT32      PCITopAddress;               //364
 306
 307   UINT32      LDMA1Addr;                   // 368
 308   UINT32      LDMA1Len;                    // 372
 309   UINT32      LDMA11Addr;                  // 376
 310   UINT32      LDMA11Len;                   // 380
 311   UINT32      PWM1Addr;                    // 384 PWM1
 312   UINT32      PWM1Len;                     // 388
 313   UINT32      PWM11Addr;                   // 392
 314   UINT32      PWM11Len;                    // 396
 315   UINT32      PWM2Addr;                    // 400 PWM2
 316   UINT32      PWM2Len;                     // 404
 317   UINT32      PWM21Addr;                   // 408
 318   UINT32      PWM21Len;                    // 412
 319   UINT32      UART1Addr;                   // 416 UART1
 320   UINT32      UART1Len;                    // 420
 321   UINT32      UART11Addr;                  // 424 UART1
 322   UINT32      UART11Len;                   // 428
 323   UINT32      UART2Addr;                   // 432 UART2
 324   UINT32      UART2Len;                    // 436
 325   UINT32      UART21Addr;                  // 440 UART2
 326   UINT32      UART21Len;                   // 444
 327   UINT32      SPIAddr;                     // 448 SPI
 328   UINT32      SPILen;                      // 452
 329   UINT32      SPI1Addr;                    // 456
 330   UINT32      SPI1Len;                     // 460
 331
 332   UINT32      LDMA2Addr;                   // 464
 333   UINT32      LDMA2Len;                    // 468
 334   UINT32      LDMA21Addr;                  // 472
 335   UINT32      LDMA21Len;                   // 476
 336   UINT32      I2C1Addr;                    // 480 I2C1
 337   UINT32      I2C1Len;                     // 484
 338   UINT32      I2C11Addr;                   // 488 I2C1
 339   UINT32      I2C11Len;                    // 492
 340   UINT32      I2C2Addr;                    // 496 I2C2
 341   UINT32      I2C2Len;                     // 500
 342   UINT32      I2C21Addr;                   // 504 I2C2
 343   UINT32      I2C21Len;                    // 508
 344   UINT32      I2C3Addr;                    // 512 I2C3
 345   UINT32      I2C3Len;                     // 516
 346   UINT32      I2C31Addr;                   // 520 I2C3
 347   UINT32      I2C31Len;                    // 524
 348   UINT32      I2C4Addr;                    // 528 I2C4
 349   UINT32      I2C4Len;                     // 532
 350   UINT32      I2C41Addr;                   // 536 I2C4
 351   UINT32      I2C41Len;                    // 540
 352   UINT32      I2C5Addr;                    // 544 I2C5
 353   UINT32      I2C5Len;                     // 548
 354   UINT32      I2C51Addr;                   // 552 I2C5
 355   UINT32      I2C51Len;                    // 556
 356   UINT32      I2C6Addr;                    // 560 I2C6
 357   UINT32      I2C6Len;                     // 564
 358   UINT32      I2C61Addr;                   // 566 I2C6
 359   UINT32      I2C61Len;                    // 570
 360   UINT32      I2C7Addr;                    // 574 I2C7
 361   UINT32      I2C7Len;                     // 578
 362   UINT32      I2C71Addr;                   // 582 I2C7
 363   UINT32      I2C71Len;                    // 586
 364
 365   //
 366   // Scc controllers
 367   //
 368   UINT32      eMMCAddr;                    // 590 EMMC
 369   UINT32      eMMCLen;                     // 594
 370   UINT32      eMMC1Addr;                   // 598
 371   UINT32      eMMC1Len;                    // 602
 372   UINT32      SDIOAddr;                    // 606 SDIO
 373   UINT32      SDIOLen;                     // 610
 374   UINT32      SDIO1Addr;                   // 614
 375   UINT32      SDIO1Len;                    // 618
 376   UINT32      SDCardAddr;                  // 622 SDCard
 377   UINT32      SDCardLen;                   // 626
 378   UINT32      SDCard1Addr;                 // 630
 379   UINT32      SDCard1Len;                  // 636
 380   UINT32      MipiHsiAddr;                 // 640 MIPI-HSI
 381   UINT32      MipiHsiLen;                  // 644
 382   UINT32      MipiHsi1Addr;                // 648
 383   UINT32      MipiHsi1Len;                 // 652
 384
 385   UINT8       SdCardRemovable;                   // 656 reserve offset upto 658
 386   UINT8       HideLPSSDevices;                   // 657 Hide unsupported LPSS devices when in ACPI mode
 387   UINT8       ReservedO;                         // 658 OS Selection
 388   UINT8       Reserved00;                        // 659
 389   UINT8       Reserved01;                        // 660
 390   UINT8       Reserved02;                   // 661
 391   UINT8       Reserved03;                   // 662
 392   UINT8       Reserved04;                   // 663
 393   UINT8       Reserved05;                   // 664
 394   UINT8       Reserved06;                   // 665
 395   UINT8       Reserved07;                       // 666
 396   UINT8       Reserved08;                 // 667
 397   UINT8       Reserved09;                     // 668
 398   UINT8       Reserved0A;                     // 669
 399   UINT32      Reserved0B;       // 670
 400   UINT32      Reserved0C;        // 674
 401   UINT32      Reserved0D;   // 678
 402   UINT32      Reserved0E;    // 682
 403   UINT32      Reserved0F;   // 686
 404   UINT32      Reserved10;    // 690
 405   UINT32      Reserved11;   // 694
 406   UINT32      Reserved12;    // 698
 407   UINT32      Reserved13;   // 702
 408   UINT32      Reserved14;    // 706
 409   UINT32      Reserved15;   // 710
 410   UINT32      Reserved16;    // 714
 411   UINT8       Reserved17;
 412   UINT32      Reserved18;
 413   UINT32      Reserved19;
 414   UINT32      Reserved1A;
 415   UINT32      Reserved1B;
 416   UINT32      Reserved1C;
 417   UINT8       Reserved1D;
 418   UINT32      Reserved1E;
 419   UINT32      Reserved1F;
 420   UINT32      Reserved20;
 421   UINT32      Reserved21;
 422   UINT32      Reserved22;
 423   UINT8       Reserved23;
 424   UINT8       BatteryChargingSolution;           // 761 0-non ULPMC 1-ULPMC
 425
 426   //
 427   //101 bytes
 428   //
 429   UINT8       NFCnSelect;                        // 762 NFCx Select 1: NFC1    2:NFC2
 430   UINT8       LpssSccMode;                       // 763 EMMC device 0-ACPI mode, 1-PCI mode
 431
 432   UINT32      TPMAddress;                        // 764
 433   UINT32      TPMLength;                         // 768
 434
 435   UINT8       I2CTouchAddress;                   // 772 I2C touch address, 0x4B:RVP   0x4A:FFRD
 436   UINT8       IdleReserve;                       // 773  0 - disabled 1 - enabled
 437   UINT8       SDIOMode;                          // 774  3 - Default  2 - DDR50
 438   UINT8       emmcVersion;                       // 775  0 - 4.41 1 - 4.5
 439   UINT32      BmBound;                           // 776 BM Bound
 440   UINT8       FsaStatus;                         // 780 0 - Fsa is off, 1- Fsa is on
 441
 442   //
 443   // Board Id
 444   // This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc
 445   //
 446   UINT8       BoardID;                           //  781
 447   UINT8       FabID;                             // 782
 448   UINT8       OtgMode;                           // 783 0- OTG disable 1- OTG PCI mode
 449   UINT8       Stepping;                          //  784 Stepping
 450   UINT8       WittEnable;                        // 785 WITT eanble 0 - disable 1 - enable
 451
 452   UINT8       SocStepping;                       // 786 Soc Stepping infomation
 453   UINT8       AmbientTripPointChange;            // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
 454   UINT8       UtsEnable;                         // 788 Uart Test eanble 0 - disable 1 - enable
 455   UINT8     DptfReserve;       // 789
 456
 457   UINT8       SarEnable;                          // 790
 458   UINT8       PssDeveice;                        // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K
 459   UINT8       EDPV;                              // 792 Check for eDP display device
 460   UINT32      DIDX;                              // 793 Device ID for eDP device
 461   UINT8       MicrosoftIoT;                      // (794)JP1 pins are for Microsoft IoT project.
 462   UINT8       RtcBattery;                        // (795) The Flag of RTC Battery Present.
 463   UINT8       LpeAudioReportedByDSDT;            // (796)
 464 } EFI_GLOBAL_NVS_AREA;
 465 #pragma pack ()
 466
 467 //
 468 // Global NVS Area Protocol
 469 //
 470 typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
 471   EFI_GLOBAL_NVS_AREA     *Area;
 472 } EFI_GLOBAL_NVS_AREA_PROTOCOL;
 473
 474 #endif
 475