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1 /*++
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7
8
9
10 Module Name:
11
12 LpcWpc83667Policy.h
13
14 Abstract:
15
16 Protocol used for WPC83627 Policy definition.
17 -------------------------------------------------------------------------------
18 Rev Date<MM/DD/YYYY> Name Description
19 -------------------------------------------------------------------------------
20 R01 < 4/22/2011> LB Update driver for Sio83627UGH support.
21 -------------------------------------------------------------------------------
22 **/
23
24 #ifndef _WPC83627_POLICY_PROTOCOL_H_
25 #define _WPC83627_POLICY_PROTOCOL_H_
26
27 EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL);
28
29 #define EFI_WPC83627_POLICY_PROTOCOL_GUID \
30 { \
31 0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d \
32 }
33
34 #define EFI_WPC83627_COM1_ENABLE 0x01
35 #define EFI_WPC83627_COM2_ENABLE 0x01
36
37 #define EFI_WPC83627_COM3_ENABLE 0x01
38 #define EFI_WPC83627_COM4_ENABLE 0x01
39
40 #define EFI_WPC83627_LPT1_ENABLE 0x01
41 #define EFI_WPC83627_LPT1_ENABLE 0x01
42 #define EFI_WPC83627_FDD_ENABLE 0x01
43 #define EFI_WPC83627_FDD_WRITE_ENABLE 0x01
44 #define EFI_WPC83627_PS2_KBC_ENABLE 0x01
45 #define EFI_WPC83627_ECIR_ENABLE 0x01
46
47 #define EFI_WPC83627_COM1_DISABLE 0x00
48 #define EFI_WPC83627_COM2_DISABLE 0x00
49
50 #define EFI_WPC83627_COM3_DISABLE 0x00
51 #define EFI_WPC83627_COM4_DISABLE 0x00
52
53 #define EFI_WPC83627_LPT1_DISABLE 0x00
54 #define EFI_WPC83627_FDD_DISABLE 0x00
55 #define EFI_WPC83627_FDD_WRITE_PROTECT 0x00
56 #define EFI_WPC83627_PS2_KBC_DISABLE 0x00
57 #define EFI_WPC83627_ECIR_DISABLE 0x00
58 #define EFI_WPC83627_RESERVED_DEFAULT 0x00
59
60 typedef struct {
61 UINT16 Com1 :1; // 0 = Disable, 1 = Enable
62 UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable
63 UINT16 Floppy :1; // 0 = Disable, 1 = Enable
64 UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable
65 UINT16 Port80 :1; // 0 = Disable, 1 = Enable
66 UINT16 CIR :1; // CIR enable or disable
67 UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable
68 UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable
69 UINT16 Com2 :1; // 0 = Disable, 1 = Enable
70
71 UINT16 Com3 :1; // 0 = Disable, 1 = Enable
72 UINT16 Com4 :1; // 0 = Disable, 1 = Enable
73
74 UINT16 Dac :1; // 0 = Disable, 1 = Enable
75 UINT16 Rsvd :6;
76 } EFI_WPC83627_DEVICE_ENABLES;
77
78 typedef enum {
79 LptModeOutput,
80 LptModeBiDirectional,
81 LptModeEpp,
82 LptModeEcp
83 } EFI_LPT_MODE;
84
85 typedef struct _EFI_WPC83627_POLICY_PROTOCOL {
86 EFI_WPC83627_DEVICE_ENABLES DeviceEnables;
87 EFI_LPT_MODE LptMode;
88 } EFI_WPC83627_POLICY_PROTOCOL;
89
90 extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid;
91
92 #endif