Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c

   1 /*++
   2
   3 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9
  10 Module Name:
  11
  12   EfiRegTableLib.c
  13
  14 Abstract:
  15
  16   Lib function for table driven register initialization.
  17
  18 Revision History
  19
  20 --*/
  21
  22 #include <Library/EfiRegTableLib.h>
  23 #include <Library/S3BootScriptLib.h>
  24
  25 //
  26 // Local Functions
  27 //
  28
  29 /**
  30   Local worker function to process PCI_WRITE table entries.  Performs write and
  31   may also call BootScriptSave protocol if indicated in the Entry flags
  32
  33   @param Entry            A pointer to the PCI_WRITE entry to process
  34
  35   @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used
  36                           when processing the entry.
  37
  38   @retval Nothing.
  39
  40 **/
  41 STATIC
  42 VOID
  43 PciWrite (
  44   EFI_REG_TABLE_PCI_WRITE             *Entry,
  45   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo
  46   )
  47 {
  48   EFI_STATUS  Status;
  49
  50   Status = PciRootBridgeIo->Pci.Write (
  51                                   PciRootBridgeIo,
  52                                   (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
  53                                   (UINT64) Entry->PciAddress,
  54                                   1,
  55                                   &Entry->Data
  56                                   );
  57   ASSERT_EFI_ERROR (Status);
  58
  59   if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
  60     Status = S3BootScriptSavePciCfgWrite (
  61               (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
  62               (UINT64) Entry->PciAddress,
  63               1,
  64               &Entry->Data
  65               );
  66     ASSERT_EFI_ERROR (Status);
  67   }
  68 }
  69
  70 /**
  71   Local worker function to process PCI_READ_MODIFY_WRITE table entries.
  72   Performs RMW write and may also call BootScriptSave protocol if indicated in
  73   the Entry flags.
  74
  75   @param Entry            A pointer to the PCI_READ_MODIFY_WRITE entry to process.
  76
  77   @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used
  78                           when processing the entry.
  79
  80   @retval Nothing.
  81
  82 **/
  83 STATIC
  84 VOID
  85 PciReadModifyWrite (
  86   EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,
  87   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo
  88   )
  89 {
  90   EFI_STATUS  Status;
  91   UINT32      TempData;
  92
  93   Status = PciRootBridgeIo->Pci.Read (
  94                                   PciRootBridgeIo,
  95                                   (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
  96                                   (UINT64) Entry->PciAddress,
  97                                   1,
  98                                   &TempData
  99                                   );
 100   ASSERT_EFI_ERROR (Status);
 101
 102   Entry->OrMask &= Entry->AndMask;
 103   TempData &= ~Entry->AndMask;
 104   TempData |= Entry->OrMask;
 105
 106   Status = PciRootBridgeIo->Pci.Write (
 107                                   PciRootBridgeIo,
 108                                   (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
 109                                   (UINT64) Entry->PciAddress,
 110                                   1,
 111                                   &TempData
 112                                   );
 113   ASSERT_EFI_ERROR (Status);
 114
 115   if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
 116     Status = S3BootScriptSavePciCfgReadWrite (
 117               (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
 118               (UINT64) Entry->PciAddress,
 119               &Entry->OrMask,
 120               &Entry->AndMask
 121               );
 122     ASSERT_EFI_ERROR (Status);
 123   }
 124 }
 125
 126 /**
 127   Local worker function to process MEM_READ_MODIFY_WRITE table entries.
 128   Performs RMW write and may also call BootScriptSave protocol if indicated in
 129   the Entry flags.
 130
 131   @param Entry            A pointer to the MEM_READ_MODIFY_WRITE entry to process.
 132
 133   @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used
 134                           when processing the entry.
 135
 136   @retval Nothing.
 137
 138 **/
 139 STATIC
 140 VOID
 141 MemReadModifyWrite (
 142   EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,
 143   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo
 144   )
 145 {
 146   EFI_STATUS  Status;
 147   UINT32      TempData;
 148
 149   Status = PciRootBridgeIo->Mem.Read (
 150                                   PciRootBridgeIo,
 151                                   (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
 152                                   (UINT64) Entry->MemAddress,
 153                                   1,
 154                                   &TempData
 155                                   );
 156   ASSERT_EFI_ERROR (Status);
 157
 158   Entry->OrMask &= Entry->AndMask;
 159   TempData &= ~Entry->AndMask;
 160   TempData |= Entry->OrMask;
 161
 162   Status = PciRootBridgeIo->Mem.Write (
 163                                   PciRootBridgeIo,
 164                                   (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
 165                                   (UINT64) Entry->MemAddress,
 166                                   1,
 167                                   &TempData
 168                                   );
 169   ASSERT_EFI_ERROR (Status);
 170
 171   if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {
 172     Status = S3BootScriptSaveMemReadWrite (
 173               (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),
 174               Entry->MemAddress,
 175               &Entry->OrMask,
 176               &Entry->AndMask
 177               );
 178     ASSERT_EFI_ERROR (Status);
 179   }
 180 }
 181
 182 //
 183 // Exported functions
 184 //
 185
 186 /**
 187   Processes register table assuming which may contain PCI, IO, MEM, and STALL
 188   entries.
 189
 190   No parameter checking is done so the caller must be careful about omitting
 191   values for PciRootBridgeIo or CpuIo parameters.  If the regtable does
 192   not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
 193   NULL).  If the regtable does not contain any IO or Mem entries, it is safe to
 194   omit the CpuIo (supply NULL).
 195
 196   The RegTableEntry parameter is not checked, but is required.
 197
 198   gBS is assumed to have been defined and is used when processing stalls.
 199
 200   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 201   entry is encountered.
 202
 203   @param RegTableEntry    A pointer to the register table to process
 204
 205   @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used
 206                           when processing PCI table entries
 207
 208   @param CpuIo            A pointer to the instance of CpuIo that is used when processing IO and
 209                           MEM table entries
 210
 211   @retval Nothing.
 212
 213 **/
 214 VOID
 215 ProcessRegTablePci (
 216   EFI_REG_TABLE                       *RegTableEntry,
 217   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo,
 218   EFI_CPU_IO_PROTOCOL                 *CpuIo
 219   )
 220 {
 221   while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
 222     switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
 223     case OP_PCI_WRITE:
 224       PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);
 225       break;
 226
 227     case OP_PCI_READ_MODIFY_WRITE:
 228       PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
 229       break;
 230
 231     case OP_MEM_READ_MODIFY_WRITE:
 232       MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);
 233       break;
 234
 235     default:
 236       DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
 237       ASSERT (0);
 238       break;
 239     }
 240
 241     RegTableEntry++;
 242   }
 243 }
 244
 245 /**
 246   Processes register table assuming which may contain IO, MEM, and STALL
 247   entries, but must NOT contain any PCI entries.  Any PCI entries cause an
 248   ASSERT in a DEBUG build and are skipped in a free build.
 249
 250   No parameter checking is done.  Both RegTableEntry and CpuIo parameters are
 251   required.
 252
 253   gBS is assumed to have been defined and is used when processing stalls.
 254
 255   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 256   entry is encountered.
 257
 258   @param  RegTableEntry   A pointer to the register table to process
 259
 260   @param  CpuIo           A pointer to the instance of CpuIo that is used when processing IO and
 261                           MEM table entries
 262
 263   @retval Nothing.
 264
 265 **/
 266 VOID
 267 ProcessRegTableCpu (
 268   EFI_REG_TABLE                       *RegTableEntry,
 269   EFI_CPU_IO_PROTOCOL                 *CpuIo
 270   )
 271 {
 272   while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {
 273     switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {
 274     default:
 275       DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));
 276       ASSERT (0);
 277       break;
 278     }
 279
 280     RegTableEntry++;
 281   }
 282 }