Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 **/
  16
  17 #include <Library/SpiFlash.H>
  18
  19 #define FLASH_SIZE  0x300000
  20 #define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)
  21
  22 //
  23 // Serial Flash device initialization data table provided to the
  24 // Intel(R) SPI Host Controller Compatibility Interface.
  25 //
  26 SPI_INIT_TABLE  mInitTable[] = {
  27   {
  28   SF_VENDOR_ID_WINBOND,     // VendorId
  29   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
  30   SF_DEVICE_ID1_W25Q64,     // DeviceId 1
  31   {
  32     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  33     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
  34   },
  35   {
  36     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  37     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  38     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  39     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
  40     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
  41     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
  42     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
  43     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
  44   },
  45
  46   //
  47   // The offset of the start of the BIOS image in flash. This value is platform specific
  48   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
  49   //
  50   ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
  51
  52   //
  53   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
  54   //
  55   FLASH_SIZE
  56   },
  57   {
  58   SF_VENDOR_ID_ATMEL,       // VendorId
  59   SF_DEVICE_ID0_AT25DF321A,  // DeviceId 0
  60   SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
  61   {
  62     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  63     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
  64   },
  65   {
  66     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  67     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  68     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  69     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
  70     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
  71     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
  72     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
  73     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
  74   },
  75
  76   //
  77   // The offset of the start of the BIOS image in flash. This value is platform specific
  78   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
  79   //
  80   ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),
  81
  82   //
  83   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
  84   //
  85   FLASH_SIZE
  86   },
  87   {
  88   SF_VENDOR_ID_ATMEL,       // VendorId
  89   SF_DEVICE_ID0_AT26DF321,  // DeviceId 0
  90   SF_DEVICE_ID1_AT26DF321,  // DeviceId 1
  91   {
  92     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  93     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
  94   },
  95   {
  96     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  97     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  98     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  99     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 100     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 101     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 102     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 103     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 104   },
 105
 106   //
 107   // The offset of the start of the BIOS image in flash. This value is platform specific
 108   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 109   //
 110   ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),
 111
 112   //
 113   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 114   //
 115   FLASH_SIZE
 116   },
 117   {
 118   SF_VENDOR_ID_ATMEL,       // VendorId
 119   SF_DEVICE_ID0_AT25DF641,  // DeviceId 0
 120   SF_DEVICE_ID1_AT25DF641,  // DeviceId 1
 121   {
 122     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 123     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 124   },
 125   {
 126     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 127     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 128     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 129     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 130     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 131     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 132     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 133     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 134   },
 135
 136   //
 137   // The offset of the start of the BIOS image in flash. This value is platform specific
 138   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 139   //
 140   ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),
 141
 142   //
 143   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 144   //
 145   FLASH_SIZE
 146   },
 147   {
 148   SF_VENDOR_ID_WINBOND,     // VendorId
 149   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 150   SF_DEVICE_ID1_W25Q16,     // DeviceId 1
 151   {
 152     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 153     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 154   },
 155   {
 156     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 157     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 158     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 159     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 160     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 161     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 162     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 163     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 164   },
 165
 166   //
 167   // The offset of the start of the BIOS image in flash. This value is platform specific
 168   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 169   //
 170   ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 171
 172   //
 173   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 174   //
 175   FLASH_SIZE
 176   },
 177   {
 178   SF_VENDOR_ID_WINBOND,     // VendorId
 179   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 180   SF_DEVICE_ID1_W25Q32,     // DeviceId 1
 181   {
 182     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 183     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register.
 184   },
 185   {
 186     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 187     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 188     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 189     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 190     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 191     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 192     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 193     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 194   },
 195
 196   //
 197   // The offset of the start of the BIOS image in flash. This value is platform specific
 198   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 199   //
 200   ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 201
 202   //
 203   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 204   //
 205   FLASH_SIZE
 206   },
 207   {
 208   SF_VENDOR_ID_WINBOND,     // VendorId
 209   SF_DEVICE_ID0_W25XXX,     // DeviceId 0
 210   SF_DEVICE_ID1_W25X32,     // DeviceId 1
 211   {
 212     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 213     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 214   },
 215   {
 216     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 217     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 218     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 219     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 220     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 221     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 222     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 223     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 224   },
 225
 226   //
 227   // The offset of the start of the BIOS image in flash. This value is platform specific
 228   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 229   //
 230   ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 231
 232   //
 233   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 234   //
 235   FLASH_SIZE
 236   },
 237   {
 238   SF_VENDOR_ID_WINBOND,     // VendorId
 239   SF_DEVICE_ID0_W25XXX,     // DeviceId 0
 240   SF_DEVICE_ID1_W25X64,     // DeviceId 1
 241   {
 242     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 243     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 244   },
 245   {
 246     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },     // Opcode 0: Read ID
 247     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },     // Opcode 1: Read
 248     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },     // Opcode 2: Read Status Register
 249     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 250     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },     // Opcode 4: Sector Erase (4KB)
 251     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },     // Opcode 5: Block Erase (64KB
 252     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},    // Opcode 6: Byte Program
 253     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },     // Opcode 7: Write Status Register
 254   },
 255
 256   //
 257   // The offset of the start of the BIOS image in flash. This value is platform specific
 258   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 259   //
 260   ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 261
 262   //
 263   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 264   //
 265   FLASH_SIZE
 266   },
 267   {
 268   SF_VENDOR_ID_WINBOND,     // VendorId
 269   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 270   SF_DEVICE_ID1_W25Q128,    // DeviceId 1
 271   {
 272     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 273     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 274   },
 275   {
 276     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 277     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 278     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 279     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 280     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 281     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 282     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 283     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 284   },
 285
 286   //
 287   // The offset of the start of the BIOS image in flash. This value is platform specific
 288   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 289   //
 290   ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 291
 292   //
 293   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 294   //
 295   FLASH_SIZE
 296   },
 297   {
 298   SF_VENDOR_ID_MACRONIX,    // VendorId
 299   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 300   SF_DEVICE_ID1_MX25L16,    // DeviceId 1
 301   {
 302     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 303     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).
 304   },
 305   {
 306     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 307     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 308     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 309     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 310     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 311     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 312     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 313     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 314   },
 315
 316   //
 317   // The offset of the start of the BIOS image in flash. This value is platform specific
 318   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 319   //
 320   ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 321
 322   //
 323   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 324   //
 325   FLASH_SIZE
 326   },
 327   {
 328   SF_VENDOR_ID_MACRONIX,    // VendorId
 329   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 330   SF_DEVICE_ID1_MX25L32,    // DeviceId 1
 331   {
 332     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 333     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).
 334   },
 335   {
 336     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 337     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 338     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 339     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 340     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 341     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 342     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 343     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 344   },
 345
 346   //
 347   // The offset of the start of the BIOS image in flash. This value is platform specific
 348   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 349   //
 350   ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 351
 352   //
 353   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 354   //
 355   FLASH_SIZE
 356   },
 357   {
 358   SF_VENDOR_ID_MACRONIX,    // VendorId
 359   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 360   SF_DEVICE_ID1_MX25L64,    // DeviceId 1
 361   {
 362     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 363     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 364   },
 365   {
 366     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 367     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 368     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 369     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 370     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 371     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 372     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 373     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 374   },
 375
 376   //
 377   // The offset of the start of the BIOS image in flash. This value is platform specific
 378   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 379   //
 380   ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 381
 382   //
 383   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 384   //
 385   FLASH_SIZE
 386   },
 387   {
 388   SF_VENDOR_ID_MACRONIX,    // VendorId
 389   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 390   SF_DEVICE_ID1_MX25L128,   // DeviceId 1
 391   {
 392     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 393     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 394   },
 395   {
 396     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 397     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 398     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 399     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 400     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 401     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 402     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 403     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 404   },
 405
 406   //
 407   // The offset of the start of the BIOS image in flash. This value is platform specific
 408   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 409   //
 410   ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 411
 412   //
 413   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 414   //
 415   FLASH_SIZE
 416   },
 417   {
 418   SF_VENDOR_ID_MACRONIX,          // VendorId
 419   SF_DEVICE_ID0_MX25UXX,          // DeviceId 0
 420   SF_DEVICE_ID1_MX25U6435F,   // DeviceId 1
 421   {
 422     SF_INST_WREN,                     // Prefix Opcode 0: Write Enable
 423     SF_INST_EWSR                          // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 424   },
 425   {
 426     {EnumSpiOpcodeReadNoAddr,   SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId              },              // Opcode 0: Read ID
 427     {EnumSpiOpcodeRead,                 SF_INST_READ,                   EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 428     {EnumSpiOpcodeReadNoAddr,   SF_INST_RDSR,                   EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 429     {EnumSpiOpcodeRead,                 SF_INST_SFDP,                   EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},        // Opcode 3: Serial Flash Discovery Parameters
 430     {EnumSpiOpcodeWrite,                SF_INST_SERASE,                 EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 431     {EnumSpiOpcodeWrite,                SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 432     {EnumSpiOpcodeWrite,                SF_INST_PROG,                   EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},         // Opcode 6: Byte Program
 433     {EnumSpiOpcodeWriteNoAddr,  SF_INST_WRSR,                   EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 434   },
 435
 436   //
 437   // The offset of the start of the BIOS image in flash. This value is platform specific
 438   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 439   //
 440   ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 441
 442   //
 443   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 444   //
 445   FLASH_SIZE
 446   },
 447   {
 448   SF_VENDOR_ID_SST,         // VendorId
 449   SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
 450   SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
 451   {
 452     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 453     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 454   },
 455   {
 456     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 457     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 458     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 459     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 460     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 461     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 462     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 463     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 464   },
 465
 466   //
 467   // The offset of the start of the BIOS image in flash. This value is platform specific
 468   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 469   //
 470   ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),
 471
 472   //
 473   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 474   //
 475   FLASH_SIZE
 476   },
 477   {
 478   SF_VENDOR_ID_SST,         // VendorId
 479   SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
 480   SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
 481   {
 482     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 483     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 484   },
 485   {
 486     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 487     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 488     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 489     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 490     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 491     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 492     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 493     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 494   },
 495
 496   //
 497   // The offset of the start of the BIOS image in flash. This value is platform specific
 498   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 499   //
 500   ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),
 501
 502   //
 503   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 504   //
 505   FLASH_SIZE
 506   },
 507   {
 508         //
 509         // Minnow2 SPI type
 510         //
 511   SF_VENDOR_ID_NUMONYX,     // VendorId
 512   SF_DEVICE_ID0_N25Q064,    // DeviceId 0
 513   SF_DEVICE_ID1_N25Q064,    // DeviceId 1
 514   {
 515     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 516     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 517   },
 518   {
 519     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle20MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 520     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 521     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle20MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 522     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle20MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 523     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 524     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 525     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 526     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle20MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 527   },
 528
 529   //
 530   // The offset of the start of the BIOS image in flash. This value is platform specific
 531   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 532   //
 533   ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
 534
 535   //
 536   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 537   //
 538   FLASH_SIZE
 539   },
 540   {
 541   SF_VENDOR_ID_NUMONYX,     // VendorId
 542   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 543   SF_DEVICE_ID1_M25PX16,    // DeviceId 1
 544   {
 545     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 546     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 547   },
 548   {
 549     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 550     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 551     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 552     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 553     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 554     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 555     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 556     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 557   },
 558
 559   //
 560   // The offset of the start of the BIOS image in flash. This value is platform specific
 561   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 562   //
 563   ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 564
 565   //
 566   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 567   //
 568   FLASH_SIZE
 569   },
 570   {
 571   SF_VENDOR_ID_NUMONYX,     // VendorId
 572   SF_DEVICE_ID0_N25QXXX,    // DeviceId 0
 573   SF_DEVICE_ID1_N25Q032,    // DeviceId 1
 574   {
 575     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 576     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 577   },
 578   {
 579     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },        // Opcode 0: Read ID
 580     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },        // Opcode 1: Read
 581     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },        // Opcode 2: Read Status Register
 582     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 583     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 584     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 585     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},   // Opcode 6: Byte Program
 586     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 587   },
 588
 589   //
 590   // The offset of the start of the BIOS image in flash. This value is platform specific
 591   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 592   //
 593   ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),
 594
 595   //
 596   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 597   //
 598   FLASH_SIZE
 599   },
 600   {
 601   SF_VENDOR_ID_NUMONYX,     // VendorId
 602   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 603   SF_DEVICE_ID1_M25PX32,    // DeviceId 1
 604   {
 605     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 606     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 607   },
 608   {
 609     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 610     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 611     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 612     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 613     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 614     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 615     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 616     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 617   },
 618
 619   //
 620   // The offset of the start of the BIOS image in flash. This value is platform specific
 621   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 622   //
 623   ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 624
 625   //
 626   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 627   //
 628   FLASH_SIZE
 629   },
 630   {
 631   SF_VENDOR_ID_NUMONYX,     // VendorId
 632   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 633   SF_DEVICE_ID1_M25PX64,    // DeviceId 1
 634   {
 635     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 636     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 637   },
 638   {
 639     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 640     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 641     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 642     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 643     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 644     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 645     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 646     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 647   },
 648
 649   //
 650   // The offset of the start of the BIOS image in flash. This value is platform specific
 651   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 652   //
 653   ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 654
 655   //
 656   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 657   //
 658   FLASH_SIZE
 659   },
 660   {
 661   SF_VENDOR_ID_NUMONYX,     // VendorId
 662   SF_DEVICE_ID0_N25QXXX,    // DeviceId 0
 663   SF_DEVICE_ID1_N25Q128,    // DeviceId 1
 664   {
 665     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 666     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 667   },
 668   {
 669     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 670     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 671     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 672     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 673     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 674     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 675     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 676     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 677   },
 678
 679   //
 680   // The offset of the start of the BIOS image in flash. This value is platform specific
 681   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 682   //
 683   ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 684
 685   //
 686   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 687   //
 688   FLASH_SIZE
 689   },
 690   {
 691   SF_VENDOR_ID_EON,         // VendorId
 692   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 693   SF_DEVICE_ID1_EN25Q16,    // DeviceId 1
 694   {
 695     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 696     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 697   },
 698   {
 699     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 700     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 701     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 702     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 703     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 704     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 705     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 706     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 707   },
 708
 709   //
 710   // The offset of the start of the BIOS image in flash. This value is platform specific
 711   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 712   //
 713   ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 714
 715   //
 716   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 717   //
 718   FLASH_SIZE
 719   },
 720   {
 721   SF_VENDOR_ID_EON,         // VendorId
 722   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 723   SF_DEVICE_ID1_EN25Q32,    // DeviceId 1
 724   {
 725     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 726     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 727   },
 728   {
 729     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 730     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 731     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 732     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 733     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 734     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 735     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 736     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 737   },
 738
 739   //
 740   // The offset of the start of the BIOS image in flash. This value is platform specific
 741   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 742   //
 743   ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 744
 745   //
 746   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 747   //
 748   FLASH_SIZE
 749   },
 750   {
 751   SF_VENDOR_ID_EON,         // VendorId
 752   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 753   SF_DEVICE_ID1_EN25Q64,    // DeviceId 1
 754   {
 755     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 756     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 757   },
 758   {
 759     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 760     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 761     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 762     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 763     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 764     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 765     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 766     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 767   },
 768
 769   //
 770   // The offset of the start of the BIOS image in flash. This value is platform specific
 771   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 772   //
 773   ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 774
 775   //
 776   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 777   //
 778   FLASH_SIZE
 779   },
 780   {
 781   SF_VENDOR_ID_EON,         // VendorId
 782   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 783   SF_DEVICE_ID1_EN25Q128,   // DeviceId 1
 784   {
 785     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 786     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 787   },
 788   {
 789     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 790     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 791     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 792     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 793     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 794     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 795     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 796     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 797   },
 798
 799   //
 800   // The offset of the start of the BIOS image in flash. This value is platform specific
 801   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 802   //
 803   ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 804
 805   //
 806   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 807   //
 808   FLASH_SIZE
 809   },
 810   {
 811   SF_VENDOR_ID_AMIC,        // VendorId
 812   SF_DEVICE_ID0_A25L016,    // DeviceId 0
 813   SF_DEVICE_ID1_A25L016,    // DeviceId 1
 814   {
 815     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 816     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 817   },
 818   {
 819     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 820     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 821     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 822     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 823     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 824     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 825     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 826     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 827   },
 828
 829   //
 830   // The offset of the start of the BIOS image in flash. This value is platform specific
 831   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 832   //
 833   ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 834
 835   //
 836   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 837   //
 838   FLASH_SIZE
 839   }
 840 };