Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h

   1 /**@file
   2   Clock generator setting for multiplatform.
   3
   4   This file includes package header files, library classes.
   5
   6   Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
   7
   8   SPDX-License-Identifier: BSD-2-Clause-Patent
   9
  10
  11 **/
  12
  13 #ifndef _BOARD_CLK_GEN_H_
  14 #define _BOARD_CLK_GEN_H_
  15
  16 #include <PiPei.h>
  17 #include <Library/HobLib.h>
  18 #include <Library/IoLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/SmbusLib.h>
  21 #include <Ppi/Smbus.h>
  22 #include <IndustryStandard/SmBus.h>
  23 #include <Guid/PlatformInfo.h>
  24
  25
  26 #define CLOCK_GENERATOR_ADDRESS  0xd2
  27
  28 #define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  29 #define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  30 #define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
  31
  32 typedef enum {
  33   ClockGeneratorCk410,
  34   ClockGeneratorCk505,
  35   ClockGeneratorMax
  36 } CLOCK_GENERATOR_TYPE;
  37
  38 typedef struct {
  39   CLOCK_GENERATOR_TYPE      ClockType;
  40   UINT8                     ClockId;
  41   UINT8                     SpreadSpectrumByteOffset;
  42   UINT8                     SpreadSpectrumBitOffset;
  43 } CLOCK_GENERATOR_DETAILS;
  44
  45 #define MAX_CLOCK_GENERATOR_BUFFER_LENGTH           0x20
  46
  47 //
  48 // CK410 Definitions
  49 //
  50 #define CK410_GENERATOR_ID                          0x65
  51 #define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE        1
  52 #define CK410_GENERATOR_SPREAD_SPECTRUM_BIT         BIT0
  53 #define CK410_GENERATOR_CLOCK_FREERUN_BYTE          4
  54 #define CK410_GENERATOR_CLOCK_FREERUN_BIT           (BIT0 | BIT1 | BIT2)
  55
  56 //
  57 // CK505 Definitions
  58 //
  59 #define VF_CK505_GENERATOR_ID                       0x5
  60 #define CK505_GENERATOR_ID                          0x5  // Confirmed readout is 5
  61 #define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE        4
  62 #define CK505_GENERATOR_SPREAD_SPECTRUM_BIT         (BIT0 | BIT1)
  63 #define CK505_GENERATOR_PERCENT_SPREAD_BYTE      1
  64 #define CK505_GENERATOR_PERCENT_MASK        ~(0xE)
  65 #define CK505_GENERATOR_PERCENT_250_VALUE      0xC
  66 #define CK505_GENERATOR_PERCENT_050_VALUE      0x4
  67 #define CK505_GENERATOR_PERCENT_000_VALUE      0x2
  68
  69 //
  70 // IDT Definitions
  71 //
  72 #define IDT_GENERATOR_ID_REVA                       0x1    //IDT Rev A
  73 #define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE        0
  74 #define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT       BIT0
  75 #define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE      5
  76 #define IDTRevA_GENERATOR_PERCENT_250_VALUE      0xF
  77 #define IDTRevA_GENERATOR_PERCENT_050_VALUE      0x3
  78 #define IDTRevA_GENERATOR_PERCENT_000_VALUE      0xE
  79 #define IDTRevA_GENERATOR_PERCENT_MASK        ~(0xF)
  80
  81 #define IDT_GENERATOR_ID_REVB                       0x11  //IDT RevB
  82 #define IDT_GENERATOR_ID_REVD                       0x21  //IDT RevD
  83
  84 //
  85 // CLOCK CONTROLLER
  86 // SmBus address to read DIMM SPD
  87 //
  88 #define SMBUS_BASE_ADDRESS                  0xEFA0
  89 #define SMBUS_BUS_DEV_FUNC                  0x1F0300
  90 #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES   4
  91 #define SMBUS_ADDR_CH_A_1                   0xA0
  92 #define SMBUS_ADDR_CH_A_2                   0xA2
  93 #define SMBUS_ADDR_CH_B_1                   0xA4
  94 #define SMBUS_ADDR_CH_B_2                   0xA6
  95
  96 //
  97 // Bits for FWH_DEC_EN1\97Firmware Hub Decode Enable Register (LPC I/F\97D31:F0)
  98 //
  99 #define   B_ICH_LPC_FWH_BIOS_DEC_F0             0x4000
 100 #define   B_ICH_LPC_FWH_BIOS_DEC_E0             0x1000
 101 #define   B_ICH_LPC_FWH_BIOS_DEC_E8             0x2000
 102 #define   B_ICH_LPC_FWH_BIOS_LEG_F              0x0080
 103 #define   B_ICH_LPC_FWH_BIOS_LEG_E              0x0040
 104
 105
 106 //
 107 // An arbitrary maximum length for clock generator buffers
 108 //
 109 #define MAX_CLOCK_GENERATOR_BUFFER_LENGTH           0x20
 110
 111 //
 112 // SmBus Bus Device Function and Register Definitions
 113 //
 114 #define SMBUS_BUS_NUM          0
 115 #define SMBUS_DEV_NUM          31
 116 #define SMBUS_FUNC_NUM          3
 117 #define SMBUS_BUS_DEV_FUNC_NUM    \
 118       SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)
 119
 120 //
 121 //ICH7: SMBus I/O Space Equates;
 122 //
 123 #define  BIT_SLAVE_ADDR    BIT00
 124 #define  BIT_COMMAND      BIT01
 125 #define  BIT_DATA      BIT02
 126 #define  BIT_COUNT      BIT03
 127 #define  BIT_WORD      BIT04
 128 #define  BIT_CONTROL      BIT05
 129 #define  BIT_PEC        BIT06
 130 #define  BIT_READ      BIT07
 131 #define  SMBUS_IO_READ_BIT  BIT00
 132
 133
 134 #define  SMB_CMD_QUICK      0x00
 135 #define  SMB_CMD_BYTE      0x04
 136 #define  SMB_CMD_BYTE_DATA    0x08
 137 #define  SMB_CMD_WORD_DATA    0x0C
 138 #define  SMB_CMD_PROCESS_CALL  0x10
 139 #define  SMB_CMD_BLOCK      0x14
 140 #define  SMB_CMD_I2C_READ    0x18
 141 #define  SMB_CMD_RESERVED    0x1c
 142
 143 #define  HST_STS_BYTE_DONE 0x80
 144 #define SMB_HST_STS    0x000
 145 #define SMB_HST_CNT    0x002
 146 #define SMB_HST_CMD    0x003
 147 #define SMB_HST_ADD    0x004
 148 #define SMB_HST_DAT_0    0x005
 149 #define SMB_HST_DAT_1    0x006
 150 #define SMB_HST_BLK_DAT   0x007
 151 #define SMB_PEC     0x008
 152 #define SMB_RCV_SLVA    0x009
 153 #define SMB_SLV_DAT    0x00A
 154 #define SMB_AUX_STS    0x00C
 155 #define SMB_AUX_CTL    0x00D
 156 #define SMB_SMLINK_PIN_CTL  0x00E
 157 #define SMB_SMBUS_PIN_CTL  0x00F
 158 #define SMB_SLV_STS    0x010
 159 #define SMB_SLV_CMD    0x011
 160 #define SMB_NTFY_DADDR    0x014
 161 #define SMB_NTFY_DLOW    0x016
 162 #define SMB_NTFY_DHIGH    0x017
 163
 164 //
 165 // PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below
 166 //
 167 #define R_COMMAND                     0x04      // PCI Command Register, 16bit
 168 #define   B_IOSE                        0x01    // RW
 169 #define R_BASE_ADDRESS                0x20      // PCI BAR for SMBus I/O
 170 #define   B_BASE_ADDRESS                0xFFE0  // RW
 171 #define R_HOST_CONFIGURATION          0x40      // SMBus Host Configuration Register
 172 #define   B_HST_EN                      0x01    // RW
 173 #define   B_SMB_SMI_EN                  0x02    // RW
 174 #define   B_I2C_EN                      0x04    // RW
 175 //
 176 // I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below
 177 //
 178 #define HOST_STATUS_REGISTER      0x00  // Host Status Register R/W
 179 #define    HST_STS_HOST_BUSY                  0x01  // RO
 180 #define   HST_STS_INTR                  0x02  // R/WC
 181 #define   HST_STS_DEV_ERR                  0x04  // R/WC
 182 #define   HST_STS_BUS_ERR                  0x08  // R/WC
 183 #define   HST_STS_FAILED                  0x10  // R/WC
 184 #define   SMBUS_B_SMBALERT_STS          0x20  // R/WC
 185 #define   HST_STS_INUSE                   0x40  // R/WC
 186 #define   SMBUS_B_BYTE_DONE_STS         0x80  // R/WC
 187 #define   SMBUS_B_HSTS_ALL              0xFF  // R/WC
 188 #define  HOST_CONTROL_REGISTER                  0x02  // Host Control Register R/W
 189 #define    HST_CNT_INTREN                0x01  // RW
 190 #define   HST_CNT_KILL                  0x02  // RW
 191 #define   SMBUS_B_SMB_CMD               0x1C  // RW
 192 #define     SMBUS_V_SMB_CMD_QUICK         0x00
 193 #define     SMBUS_V_SMB_CMD_BYTE          0x04
 194 #define     SMBUS_V_SMB_CMD_BYTE_DATA     0x08
 195 #define     SMBUS_V_SMB_CMD_WORD_DATA     0x0C
 196 #define     SMBUS_V_SMB_CMD_PROCESS_CALL  0x10
 197 #define     SMBUS_V_SMB_CMD_BLOCK         0x14
 198 #define     SMBUS_V_SMB_CMD_IIC_READ      0x18
 199 #define   SMBUS_B_LAST_BYTE             0x20  // WO
 200 #define   HST_CNT_START                 0x40  // WO
 201 #define   HST_CNT_PEC_EN                0x80  // RW
 202 #define  HOST_COMMAND_REGISTER                  0x03  // Host Command Register R/W
 203 #define  XMIT_SLAVE_ADDRESS_REGISTER                   0x04  // Transmit Slave Address Register R/W
 204 #define   SMBUS_B_RW_SEL                0x01  // RW
 205 #define   SMBUS_B_ADDRESS               0xFE  // RW
 206 #define  HOST_DATA_0_REGISTER                   0x05  // Data 0 Register R/W
 207 #define  HOST_DATA_1_REGISTER                   0x06  // Data 1 Register R/W
 208 #define  HOST_BLOCK_DATA_BYTE_REGISTER          0x07  // Host Block Data Register R/W
 209 #define SMBUS_R_PEC                   0x08  // Packet Error Check Data Register R/W
 210 #define SMBUS_R_RSA                   0x09  // Receive Slave Address Register R/W
 211 #define   SMBUS_B_SLAVE_ADDR            0x7F  // RW
 212 #define SMBUS_R_SD                    0x0A  // Receive Slave Data Register R/W
 213 #define SMBUS_R_AUXS                  0x0C  // Auxiliary Status Register R/WC
 214 #define   SMBUS_B_CRCE                  0x01  //R/WC
 215 #define AUXILIARY_CONTROL_REGISTER                  0x0D  // Auxiliary Control Register R/W
 216 #define   SMBUS_B_AAC                  0x01  //R/W
 217 #define   SMBUS_B_E32B                 0x02  //R/W
 218 #define  SMBUS_R_SMLC                  0x0E  // SMLINK Pin Control Register R/W
 219 #define   SMBUS_B_SMLINK0_CUR_STS       0x01  // RO
 220 #define   SMBUS_B_SMLINK1_CUR_STS       0x02  // RO
 221 #define   SMBUS_B_SMLINK_CLK_CTL        0x04  // RW
 222 #define SMBUS_R_SMBC                  0x0F  // SMBus Pin Control Register R/W
 223 #define   SMBUS_B_SMBCLK_CUR_STS        0x01  // RO
 224 #define   SMBUS_B_SMBDATA_CUR_STS       0x02  // RO
 225 #define   SMBUS_B_SMBCLK_CTL            0x04  // RW
 226 #define SMBUS_R_SSTS                  0x10  // Slave Status Register R/WC
 227 #define   SMBUS_B_HOST_NOTIFY_STS       0x01  // R/WC
 228 #define SMBUS_R_SCMD                  0x11  // Slave Command Register R/W
 229 #define   SMBUS_B_HOST_NOTIFY_INTREN    0x01  // R/W
 230 #define   SMBUS_B_HOST_NOTIFY_WKEN      0x02  // R/W
 231 #define   SMBUS_B_SMBALERT_DIS          0x04  // R/W
 232 #define SMBUS_R_NDA                   0x14  // Notify Device Address Register RO
 233 #define   SMBUS_B_DEVICE_ADDRESS        0xFE  // RO
 234 #define SMBUS_R_NDLB                  0x16  // Notify Data Low Byte Register RO
 235 #define SMBUS_R_NDHB                  0x17  // Notify Data High Byte Register RO
 236 #define BUS_TRIES           3       // How many times to retry on Bus Errors
 237 #define SMBUS_NUM_RESERVED  21      // Number of device addresses that are
 238                                     //   reserved by the SMBus spec.
 239 #define SMBUS_ADDRESS_ARP   0xC2 >> 1
 240 #define   SMBUS_DATA_PREPARE_TO_ARP   0x01
 241 #define   SMBUS_DATA_RESET_DEVICE     0x02
 242 #define   SMBUS_DATA_GET_UDID_GENERAL 0x03
 243 #define   SMBUS_DATA_ASSIGN_ADDRESS   0x04
 244 #define SMBUS_GET_UDID_LENGTH 17    // 16 byte UDID + 1 byte address
 245
 246
 247 EFI_STATUS
 248 ConfigurePlatformClocks (
 249   IN EFI_PEI_SERVICES           **PeiServices,
 250   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 251   IN VOID                       *SmbusPpi
 252   );
 253
 254
 255 #endif