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1 /** @file
2 Multiplatform initialization.
3
4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 **/
16
17 #include <MultiPlatformLib.h>
18
19 /**
20 Platform Type detection. Because the PEI globle variable
21 is in the flash, it could not change directly.So use
22 2 PPIs to distinguish the platform type.
23
24 @param FfsHeader Pointer to Firmware File System file header.
25 @param PeiServices General purpose services available to every PEIM.
26
27 @retval EFI_SUCCESS Memory initialization completed successfully.
28 @retval Others All other error conditions encountered result in an ASSERT.
29
30 **/
31 EFI_STATUS
32 MultiPlatformInfoInit (
33 IN CONST EFI_PEI_SERVICES **PeiServices,
34 IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
35 )
36 {
37 UINT32 PcieLength;
38
39
40 PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
41
42 PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);
43
44 //
45 // Update ICH Type
46 //
47 //
48 // Device ID
49 //
50 PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
51
52 PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
53
54 //
55 //64MB
56 //
57 PcieLength = 0x04000000;
58
59 //
60 // Don't support BASE above 4GB currently.
61 //
62 PlatformInfoHob->PciData.PciExpressSize = PcieLength;
63 PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
64
65 PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
66 PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
67
68 PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
69 PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
70 PlatformInfoHob->CpuData.CpuAddressWidth = 36;
71
72 PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
73 PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
74
75 PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
76
77 //
78 // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
79 //
80 if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
81 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
82 } else {
83 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
84 }
85 PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
86
87 //
88 // Platform PCI MMIO Size in unit of 1MB.
89 //
90 PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
91
92 //
93 // Enable ICH IOAPIC
94 //
95 PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
96
97 DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n",
98 PlatformInfoHob->PlatformFlavor,
99 FlavorTablet,
100 FlavorMobile,
101 FlavorDesktop));
102
103 //
104 // Get Platform Info and fill the Hob.
105 //
106 PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
107
108 //
109 // Get GPIO table
110 //
111 MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
112
113 //
114 // Program GPIO
115 //
116 MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
117
118 //
119 // Update OemId
120 //
121 InitializeBoardOemId (PeiServices, PlatformInfoHob);
122 InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
123
124 return EFI_SUCCESS;
125 }