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1 /** @file
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7
8
9 Module Name:
10
11 SioInit.c
12
13 Abstract:
14
15 Functions for LpcSio initialization
16
17 --*/
18
19 #include "PlatformSerialPortLib.h"
20 #include "SioInit.h"
21
22 typedef struct {
23 UINT8 Register;
24 UINT8 Value;
25 } EFI_SIO_TABLE;
26
27 EFI_SIO_TABLE mSioTableWpcn381u[] = {
28 {0x29, 0x0A0},
29 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
30 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
31 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
32 {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
33 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
34 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
35 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
36 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
37 {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
38 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
39 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
40 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
41 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
42 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
43 {0x21, 0x001}, // Global Device Enable
44 {0x26, 0x000}
45 };
46
47 EFI_SIO_TABLE mSioTableWdcp376[] = {
48 {0x29, 0x0A0},
49 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
50 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
51 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
52 {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
53 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
54 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
55 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
56 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
57 {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
58 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
59 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
60 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
61 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
62 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
63 {0x21, 0x001}, // Global Device Enable
64 {0x26, 0x000},
65 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
66 {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
67 {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
68 {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
69 {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
70 {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
71 {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
72 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
73 {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
74 {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
75 {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
76 };
77
78 /**
79 Initialization for SIO.
80
81 @param FfsHeader FV this PEIM was loaded from.
82 @param PeiServices General purpose services available to every PEIM.
83
84 None
85
86 **/
87 VOID
88 InitializeSio (
89 VOID
90 )
91 {
92 UINT16 Index;
93 UINT16 IndexPort;
94 UINT16 DataPort;
95
96 //
97 // Super I/O initialization for Winbond WPCN381U
98 //
99 IndexPort = WPCN381U_CONFIG_INDEX;
100 DataPort = WPCN381U_CONFIG_DATA;
101
102 //
103 // Check for Winbond WPCN381U
104 //
105 IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
106
107 if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
108 //
109 // Configure WPCN381U SIO
110 //
111 for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
112 IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
113 IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
114 }
115 }
116
117 if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
118 //
119 // Configure WDCP376 SIO
120 //
121 for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
122 IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
123 IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
124 }
125 }
126 return;
127 }