Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h

   1 /** @file
   2   Header file of Serial port hardware definition.
   3
   4   Copyright (c) 2012  - 2017, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available under
   7   the terms and conditions of the BSD License that accompanies this distribution.
   8   The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _SIO_INIT_H_
  17 #define _SIO_INIT_H_
  18
  19 #define WPCN381U_CONFIG_INDEX               0x2E
  20 #define WPCN381U_CONFIG_DATA                0x2F
  21 #define WPCN381U_CONFIG_INDEX1              0x164E
  22 #define WPCN381U_CONFIG_DATA1               0x164F
  23 #define WPCN381U_CHIP_ID                    0xF4
  24 #define WDCP376_CHIP_ID                     0xF1
  25
  26 //
  27 // SIO Logical Devices Numbers
  28 //
  29 #define WPCN381U_LDN_UART0                  0x03   // LDN for Serial Port Controller
  30 #define WPCN381U_LDN_UART1                  0x02   // LDN for Parallel Port Controller
  31 #define WPCN381U_LDN_PS2K                   0x06   // LDN for PS2 Keyboard Controller
  32 #define WPCN381U_LDN_PS2M                   0x05   // LDN for PS2 Mouse Controller
  33 #define WPCN381U_KB_BASE1_ADDRESS           0x60   // Base Address of KB controller
  34 #define WPCN381U_KB_BASE2_ADDRESS           0x64   // Base Address of KB controller
  35 #define SIO_KBC_CLOCK                       0x01   // 0/1/2 - 8/12/16 MHz KBC Clock Source
  36 #define WPCN381U_LDN_GPIO                   0x07   // LDN for GPIO
  37
  38 //
  39 // SIO Registers Layout
  40 //
  41 #define WPCN381U_LD_SEL_REGISTER            0x07   // Logical Device Select Register Address
  42 #define WPCN381U_DEV_ID_REGISTER            0x20   // Device Identification Register Address
  43 #define WPCN381U_ACTIVATE_REGISTER          0x30   // Device Identification Register Address
  44 #define WPCN381U_BASE1_HI_REGISTER          0x60   // Device BaseAddres Register #1 MSB Address
  45 #define WPCN381U_BASE1_LO_REGISTER          0x61   // Device BaseAddres Register #1 LSB Address
  46 #define WPCN381U_BASE2_HI_REGISTER          0x62   // Device BaseAddres Register #1 MSB Address
  47 #define WPCN381U_BASE2_LO_REGISTER          0x63   // Device Ba1eAddres Register #1 LSB Address
  48 #define WPCN381U_IRQ1_REGISTER              0x70   // Device IRQ Register #1 Address
  49 #define WPCN381U_IRQ2_REGISTER              0x71   // Device IRQ Register #2 Address
  50
  51 //
  52 // SIO Activation Values
  53 //
  54 #define WPCN381U_ACTIVATE_VALUE             0x01   // Value to activate Device
  55 #define WPCN381U_DEACTIVATE_VALUE           0x00   // Value to deactivate Device
  56
  57 //
  58 // SIO GPIO
  59 //
  60 #define WPCN381U_GPIO_BASE_ADDRESS          0x0A20 // SIO GPIO Base Address
  61
  62 //
  63 // SIO Serial Port Settings
  64 //
  65 #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS  0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
  66 #define WPCN381U_SERIAL_PORT1_BASE_ADDRESS  0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
  67
  68 #endif