Vlv2TbltDevicePkg/PlatformDxe/PciBus.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9 **/
  10
  11
  12 #ifndef _EFI_PCI_BUS_H_
  13 #define _EFI_PCI_BUS_H_
  14
  15 #include <PiDxe.h>
  16
  17 #include <Protocol/LoadedImage.h>
  18 #include <Protocol/PciHostBridgeResourceAllocation.h>
  19 #include <Protocol/PciIo.h>
  20 #include <Protocol/LoadFile2.h>
  21 #include <Protocol/PciRootBridgeIo.h>
  22 #include <Protocol/PciHotPlugRequest.h>
  23 #include <Protocol/DevicePath.h>
  24 #include <Protocol/PciPlatform.h>
  25 #include <Protocol/PciHotPlugInit.h>
  26 #include <Protocol/Decompress.h>
  27 #include <Protocol/BusSpecificDriverOverride.h>
  28 #include <Protocol/IncompatiblePciDeviceSupport.h>
  29 #include <Protocol/PciOverride.h>
  30 #include <Protocol/PciEnumerationComplete.h>
  31
  32 #include <Library/DebugLib.h>
  33 #include <Library/UefiDriverEntryPoint.h>
  34 #include <Library/BaseLib.h>
  35 #include <Library/UefiLib.h>
  36 #include <Library/BaseMemoryLib.h>
  37 #include <Library/ReportStatusCodeLib.h>
  38 #include <Library/MemoryAllocationLib.h>
  39 #include <Library/UefiBootServicesTableLib.h>
  40 #include <Library/DevicePathLib.h>
  41 #include <Library/PcdLib.h>
  42 #include <Library/PeCoffLib.h>
  43
  44 #include <IndustryStandard/Pci.h>
  45 #include <IndustryStandard/PeImage.h>
  46 #include <IndustryStandard/Acpi.h>
  47
  48 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  49 typedef struct _PCI_BAR                    PCI_BAR;
  50
  51 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  52 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  53
  54 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  55 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  56 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  57
  58 typedef enum {
  59   PciBarTypeUnknown = 0,
  60   PciBarTypeIo16,
  61   PciBarTypeIo32,
  62   PciBarTypeMem32,
  63   PciBarTypePMem32,
  64   PciBarTypeMem64,
  65   PciBarTypePMem64,
  66   PciBarTypeIo,
  67   PciBarTypeMem,
  68   PciBarTypeMaxType
  69 } PCI_BAR_TYPE;
  70
  71
  72 #define VGABASE1  0x3B0
  73 #define VGALIMIT1 0x3BB
  74
  75 #define VGABASE2  0x3C0
  76 #define VGALIMIT2 0x3DF
  77
  78 #define ISABASE   0x100
  79 #define ISALIMIT  0x3FF
  80
  81 //
  82 // PCI BAR parameters
  83 //
  84 struct _PCI_BAR {
  85   UINT64        BaseAddress;
  86   UINT64        Length;
  87   UINT64        Alignment;
  88   PCI_BAR_TYPE  BarType;
  89   BOOLEAN       Prefetchable;
  90   UINT8         MemType;
  91   UINT16        Offset;
  92 };
  93
  94 //
  95 // defined in PCI Card Specification, 8.0
  96 //
  97 #define PCI_CARD_MEMORY_BASE_0                0x1C
  98 #define PCI_CARD_MEMORY_LIMIT_0               0x20
  99 #define PCI_CARD_MEMORY_BASE_1                0x24
 100 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 101 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 102 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 103 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 104 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 105 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 106 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 107 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 108 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 109 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 110
 111 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 112 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 113
 114 #define PPB_BAR_0                             0
 115 #define PPB_BAR_1                             1
 116 #define PPB_IO_RANGE                          2
 117 #define PPB_MEM32_RANGE                       3
 118 #define PPB_PMEM32_RANGE                      4
 119 #define PPB_PMEM64_RANGE                      5
 120 #define PPB_MEM64_RANGE                       0xFF
 121
 122 #define P2C_BAR_0                             0
 123 #define P2C_MEM_1                             1
 124 #define P2C_MEM_2                             2
 125 #define P2C_IO_1                              3
 126 #define P2C_IO_2                              4
 127
 128 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 129 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 130 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 131 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 132 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 133 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 134 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 135
 136 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 137
 138 //
 139 // Define option for attribute
 140 //
 141 #define EFI_SET_SUPPORTS    0
 142 #define EFI_SET_ATTRIBUTES  1
 143
 144 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 145
 146 struct _PCI_IO_DEVICE {
 147   UINT32                                    Signature;
 148   EFI_HANDLE                                Handle;
 149   EFI_PCI_IO_PROTOCOL                       PciIo;
 150   LIST_ENTRY                                Link;
 151
 152   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 153   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 154   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 155   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 156
 157   //
 158   // PCI configuration space header type
 159   //
 160   PCI_TYPE00                                Pci;
 161
 162   //
 163   // Bus number, Device number, Function number
 164   //
 165   UINT8                                     BusNumber;
 166   UINT8                                     DeviceNumber;
 167   UINT8                                     FunctionNumber;
 168
 169   //
 170   // BAR for this PCI Device
 171   //
 172   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 173
 174   //
 175   // The bridge device this pci device is subject to
 176   //
 177   PCI_IO_DEVICE                             *Parent;
 178
 179   //
 180   // A linked list for children Pci Device if it is bridge device
 181   //
 182   LIST_ENTRY                                ChildList;
 183
 184   //
 185   // TRUE if the PCI bus driver creates the handle for this PCI device
 186   //
 187   BOOLEAN                                   Registered;
 188
 189   //
 190   // TRUE if the PCI bus driver successfully allocates the resource required by
 191   // this PCI device
 192   //
 193   BOOLEAN                                   Allocated;
 194
 195   //
 196   // The attribute this PCI device currently set
 197   //
 198   UINT64                                    Attributes;
 199
 200   //
 201   // The attributes this PCI device actually supports
 202   //
 203   UINT64                                    Supports;
 204
 205   //
 206   // The resource decode the bridge supports
 207   //
 208   UINT32                                    Decodes;
 209
 210   //
 211   // TRUE if the ROM image is from the PCI Option ROM BAR
 212   //
 213   BOOLEAN                                   EmbeddedRom;
 214
 215   //
 216   // The OptionRom Size
 217   //
 218   UINT64                                    RomSize;
 219
 220   //
 221   // The OptionRom Size
 222   //
 223   UINT64                                    RomBase;
 224
 225   //
 226   // TRUE if all OpROM (in device or in platform specific position) have been processed
 227   //
 228   BOOLEAN                                   AllOpRomProcessed;
 229
 230   //
 231   // TRUE if there is any EFI driver in the OptionRom
 232   //
 233   BOOLEAN                                   BusOverride;
 234
 235   //
 236   // A list tracking reserved resource on a bridge device
 237   //
 238   LIST_ENTRY                                ReservedResourceList;
 239
 240   //
 241   // A list tracking image handle of platform specific overriding driver
 242   //
 243   LIST_ENTRY                                OptionRomDriverList;
 244
 245   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 246   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 247
 248   BOOLEAN                                   IsPciExp;
 249
 250   //
 251   // For SR-IOV
 252   //
 253   UINT8                                     PciExpressCapabilityOffset;
 254   UINT32                                    AriCapabilityOffset;
 255   UINT32                                    SrIovCapabilityOffset;
 256   UINT32                                    MrIovCapabilityOffset;
 257   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 258   UINT32                                    SystemPageSize;
 259   UINT16                                    InitialVFs;
 260   UINT16                                    ReservedBusNum;
 261
 262   //
 263   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 264   // but some chipsets support non-standard I/O window alignments less than 4K.
 265   // This field is used to support this case.
 266   //
 267   UINT16                                    BridgeIoAlignment;
 268 };
 269
 270 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 271   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 272
 273 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 274   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 275
 276 #define PCI_IO_DEVICE_FROM_LINK(a) \
 277   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 278
 279 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 280   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 281
 282
 283
 284 //
 285 // Global Variables
 286 //
 287 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 288 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 289 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 290 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 291 extern BOOLEAN                                      gFullEnumeration;
 292 extern UINTN                                        gPciHostBridgeNumber;
 293 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 294 extern UINT64                                       gAllOne;
 295 extern UINT64                                       gAllZero;
 296 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 297 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 298 extern BOOLEAN                                      mReserveIsaAliases;
 299 extern BOOLEAN                                      mReserveVgaAliases;
 300
 301 /**
 302   Macro that checks whether device is a GFX device.
 303
 304   @param  _p      Specified device.
 305
 306   @retval TRUE    Device is a GFX device.
 307   @retval FALSE   Device is not a GFX device.
 308
 309 **/
 310 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 311
 312 /**
 313   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 314   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 315
 316   @param  This                Protocol instance pointer.
 317   @param  Controller          Handle of device to test.
 318   @param  RemainingDevicePath Optional parameter use to pick a specific child
 319                               device to start.
 320
 321   @retval EFI_SUCCESS         This driver supports this device.
 322   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 323   @retval other               This driver does not support this device.
 324
 325 **/
 326 EFI_STATUS
 327 EFIAPI
 328 PciBusDriverBindingSupported (
 329   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 330   IN EFI_HANDLE                     Controller,
 331   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 332   );
 333
 334 /**
 335   Start this driver on ControllerHandle and enumerate Pci bus and start
 336   all device under PCI bus.
 337
 338   @param  This                 Protocol instance pointer.
 339   @param  Controller           Handle of device to bind driver to.
 340   @param  RemainingDevicePath  Optional parameter use to pick a specific child
 341                                device to start.
 342
 343   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 344   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 345   @retval other                This driver does not support this device.
 346
 347 **/
 348 EFI_STATUS
 349 EFIAPI
 350 PciBusDriverBindingStart (
 351   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 352   IN EFI_HANDLE                     Controller,
 353   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 354   );
 355
 356 /**
 357   Stop this driver on ControllerHandle. Support stopping any child handles
 358   created by this driver.
 359
 360   @param  This              Protocol instance pointer.
 361   @param  Controller        Handle of device to stop driver on.
 362   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 363                             children is zero stop the entire bus driver.
 364   @param  ChildHandleBuffer List of Child Handles to Stop.
 365
 366   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 367   @retval other             This driver was not removed from this device.
 368
 369 **/
 370 EFI_STATUS
 371 EFIAPI
 372 PciBusDriverBindingStop (
 373   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 374   IN  EFI_HANDLE                    Controller,
 375   IN  UINTN                         NumberOfChildren,
 376   IN  EFI_HANDLE                    *ChildHandleBuffer
 377   );
 378
 379 #endif