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1 /** @file
2
3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
4
5
6 This program and the accompanying materials are licensed and made available under
7
8 the terms and conditions of the BSD License that accompanies this distribution.
9
10 The full text of the license may be found at
11
12 http://opensource.org/licenses/bsd-license.php.
13
14
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23 Module Name:
24
25
26 Platform.c
27
28 Abstract:
29
30 Platform Initialization Driver.
31
32
33 --*/
34
35 #include "PlatformDxe.h"
36 #include "Platform.h"
37 #include "PchCommonDefinitions.h"
38 #include <Protocol/UsbPolicy.h>
39 #include <Protocol/PchPlatformPolicy.h>
40 #include <Protocol/TpmMp.h>
41 #include <Protocol/CpuIo2.h>
42 #include <Library/S3BootScriptLib.h>
43 #include <Guid/PciLanInfo.h>
44 #include <Guid/ItkData.h>
45 #include <Library/PciLib.h>
46 #include <PlatformBootMode.h>
47 #include <Guid/EventGroup.h>
48 #include <Guid/Vlv2Variable.h>
49 #include <Protocol/GlobalNvsArea.h>
50 #include <Protocol/IgdOpRegion.h>
51 #include <Library/PcdLib.h>
52 #include <Protocol/VariableLock.h>
53
54
55 //
56 // VLV2 GPIO GROUP OFFSET
57 //
58 #define GPIO_SCORE_OFFSET 0x0000
59 #define GPIO_NCORE_OFFSET 0x1000
60 #define GPIO_SSUS_OFFSET 0x2000
61
62 typedef struct {
63 UINT32 offset;
64 UINT32 val;
65 } CFIO_PNP_INIT;
66
67 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
68 {
69 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
70 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
71 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
72 };
73
74
75 EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
76 EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
77 SYSTEM_CONFIGURATION mSystemConfiguration;
78 SYSTEM_PASSWORDS mSystemPassword;
79 EFI_HANDLE mImageHandle;
80 BOOLEAN mMfgMode = FALSE;
81 VOID *mDxePlatformStringPack;
82 UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
83 extern CHAR16 gItkDataVarName[];
84
85
86 EFI_PLATFORM_INFO_HOB mPlatformInfo;
87 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
88 EFI_EVENT mReadyToBootEvent;
89
90 UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
91 UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
92 UINT32 mSubsystemVidDid;
93 UINT32 mSubsystemAudioVidDid;
94
95 UINTN mPciLanCount = 0;
96 VOID *mPciLanInfo = NULL;
97 UINTN SpiBase;
98
99 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
100 ProgramToneFrequency,
101 GenerateBeepTone
102 };
103
104 EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
105
106
107 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
108 {
109 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
110 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
111 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
112 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
113 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
114 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
115 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
116 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
117 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
118 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
119 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
120 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
121 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
122 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
123 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
124 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
125 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
126 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
127 };
128
129 VOID
130 EfiOrMem (
131 IN VOID *Destination,
132 IN VOID *Source,
133 IN UINTN Length
134 );
135
136 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
137 STATIC
138 VOID
139 InitFirmwareId();
140 #endif
141
142
143 VOID
144 InitializeClockRouting(
145 );
146
147 VOID
148 InitializeSlotInfo (
149 );
150
151 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
152 VOID
153 InitializeSensorInfoVariable (
154 );
155 #endif
156
157 VOID
158 InitTcoReset (
159 );
160
161 VOID
162 InitExI ();
163
164 VOID
165 InitItk();
166
167 VOID
168 InitPlatformBootMode();
169
170 VOID
171 InitMfgAndConfigModeStateVar();
172
173 VOID
174 InitPchPlatformPolicy (
175 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
176 );
177
178 VOID
179 InitVlvPlatformPolicy (
180 );
181
182 VOID
183 InitSioPlatformPolicy(
184 );
185
186 VOID
187 PchInitBeforeBoot(
188 );
189
190 VOID
191 UpdateDVMTSetup(
192 );
193
194 VOID
195 InitPlatformUsbPolicy (
196 VOID
197 );
198
199 VOID
200 InitRC6Policy(
201 VOID
202 );
203
204
205 EFI_STATUS
206 EFIAPI
207 SaveSetupRecoveryVar(
208 VOID
209 )
210 {
211 EFI_STATUS Status = EFI_SUCCESS;
212 UINTN SizeOfNvStore = 0;
213 UINTN SizeOfSetupVar = 0;
214 SYSTEM_CONFIGURATION *SetupData = NULL;
215 SYSTEM_CONFIGURATION *RecoveryNvData = NULL;
216 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;
217
218
219 DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));
220 SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
221 RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
222 if (NULL == RecoveryNvData) {
223 Status = EFI_OUT_OF_RESOURCES;
224 goto Exit;
225 }
226
227 Status = gRT->GetVariable(
228 L"SetupRecovery",
229 &gEfiNormalSetupGuid,
230 NULL,
231 &SizeOfNvStore,
232 RecoveryNvData
233 );
234
235 if (EFI_ERROR (Status)) {
236 // Don't find the "SetupRecovery" variable.
237 // have to copy "Setup" variable to "SetupRecovery" variable.
238 SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
239 if (NULL == SetupData) {
240 Status = EFI_OUT_OF_RESOURCES;
241 goto Exit;
242 }
243 SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);
244 Status = gRT->GetVariable(
245 NORMAL_SETUP_NAME,
246 &gEfiNormalSetupGuid,
247 NULL,
248 &SizeOfSetupVar,
249 SetupData
250 );
251 ASSERT_EFI_ERROR (Status);
252
253 Status = gRT->SetVariable (
254 L"SetupRecovery",
255 &gEfiNormalSetupGuid,
256 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
257 sizeof(SYSTEM_CONFIGURATION),
258 SetupData
259 );
260 ASSERT_EFI_ERROR (Status);
261
262 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
263 if (!EFI_ERROR (Status)) {
264 Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery", &gEfiNormalSetupGuid);
265 ASSERT_EFI_ERROR (Status);
266 }
267
268 }
269
270 Exit:
271 if (RecoveryNvData)
272 FreePool (RecoveryNvData);
273 if (SetupData)
274 FreePool (SetupData);
275
276 return Status;
277
278 }
279
280
281 VOID
282 TristateLpcGpioConfig (
283 IN UINT32 Gpio_Mmio_Offset,
284 IN UINT32 Gpio_Pin_Num,
285 GPIO_CONF_PAD_INIT* Gpio_Conf_Data
286 )
287
288 {
289 UINT32 index;
290 UINT32 mmio_conf0;
291 UINT32 mmio_padval;
292 PAD_CONF0 conf0_val;
293 PAD_VAL pad_val;
294
295 //
296 // GPIO WELL -- Memory base registers
297 //
298
299 //
300 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
301 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
302 //
303
304 for(index=0; index < Gpio_Pin_Num; index++)
305 {
306 //
307 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
308 //
309 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
310 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
311
312 #ifdef EFI_DEBUG
313 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
314
315 #endif
316 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
317 Gpio_Conf_Data[index].usage,
318 Gpio_Conf_Data[index].func,
319 Gpio_Conf_Data[index].int_type,
320 Gpio_Conf_Data[index].pull,
321 mmio_conf0));
322
323 //
324 // Step 1: PadVal Programming
325 //
326 pad_val.dw = MmioRead32(mmio_padval);
327
328 //
329 // Config PAD_VAL only for GPIO (Non-Native) Pin
330 //
331 if(Native != Gpio_Conf_Data[index].usage)
332 {
333 pad_val.dw &= ~0x6; // Clear bits 1:2
334 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
335
336 //
337 // set GPO default value
338 //
339 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
340 {
341 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
342 }
343 }
344
345
346 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
347
348 MmioWrite32(mmio_padval, pad_val.dw);
349
350 //
351 // Step 2: CONF0 Programming
352 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
353 //
354 conf0_val.dw = MmioRead32(mmio_conf0);
355
356 //
357 // Set Function #
358 //
359 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
360
361 if(GPO == Gpio_Conf_Data[index].usage)
362 {
363 //
364 // If used as GPO, then internal pull need to be disabled
365 //
366 conf0_val.r.Pull_assign = 0; // Non-pull
367 }
368 else
369 {
370 //
371 // Set PullUp / PullDown
372 //
373 if(P_20K_H == Gpio_Conf_Data[index].pull)
374 {
375 conf0_val.r.Pull_assign = 0x1; // PullUp
376 conf0_val.r.Pull_strength = 0x2;// 20K
377 }
378 else if(P_20K_L == Gpio_Conf_Data[index].pull)
379 {
380 conf0_val.r.Pull_assign = 0x2; // PullDown
381 conf0_val.r.Pull_strength = 0x2;// 20K
382 }
383 else if(P_NONE == Gpio_Conf_Data[index].pull)
384 {
385 conf0_val.r.Pull_assign = 0; // Non-pull
386 }
387 else
388 {
389 ASSERT(FALSE); // Invalid value
390 }
391 }
392
393 //
394 // Set INT Trigger Type
395 //
396 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
397
398 //
399 // Set INT Trigger Type
400 //
401 if(TRIG_ == Gpio_Conf_Data[index].int_type)
402 {
403 //
404 // Interrupt not capable, clear bits 27:24
405 //
406 }
407 else
408 {
409 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
410 }
411
412 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
413
414 //
415 // Write back the targeted GPIO config value according to platform (board) GPIO setting
416 //
417 MmioWrite32 (mmio_conf0, conf0_val.dw);
418 }
419
420 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
421 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
422 //
423 }
424
425 VOID
426 EFIAPI
427 SpiBiosProtectionFunction(
428 EFI_EVENT Event,
429 VOID *Context
430 )
431 {
432
433 UINTN mPciD31F0RegBase;
434 UINTN BiosFlaLower0;
435 UINTN BiosFlaLimit0;
436 UINTN BiosFlaLower1;
437 UINTN BiosFlaLimit1;
438
439
440 BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
441 BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
442 #ifdef MINNOW2_FSP_BUILD
443 BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);
444 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
445 #else
446 BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
447 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
448 #endif
449
450
451 mPciD31F0RegBase = MmPciAddress (0,
452 DEFAULT_PCI_BUS_NUMBER_PCH,
453 PCI_DEVICE_NUMBER_PCH_LPC,
454 PCI_FUNCTION_NUMBER_PCH_LPC,
455 0
456 );
457 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
458
459 //
460 //Set SMM_BWP, WPD and LE bit
461 //
462 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
463 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
464 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
465
466 //
467 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
468 //
469 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
470 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
471 //
472 //Already locked. we could take no action here
473 //
474 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
475 return;
476 }
477
478 //
479 //Set PR0
480 //
481 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
482 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
483 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
484
485 //
486 //Lock down PR0
487 //
488 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
489
490 //
491 // Verify if it's really locked.
492 //
493 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
494 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
495 }
496
497 //
498 //Set PR1
499 //
500
501 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
502 B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
503 (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
504
505 //
506 //Lock down PR1
507 //
508 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
509
510 //
511 // Verify if it's really locked.
512 //
513 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
514 DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));
515 }
516 return;
517
518 }
519
520 VOID
521 EFIAPI
522 InitPciDevPME (
523 EFI_EVENT Event,
524 VOID *Context
525 )
526 {
527 UINTN VarSize;
528 EFI_STATUS Status;
529
530 VarSize = sizeof(SYSTEM_CONFIGURATION);
531 Status = gRT->GetVariable(
532 NORMAL_SETUP_NAME,
533 &gEfiNormalSetupGuid,
534 NULL,
535 &VarSize,
536 &mSystemConfiguration
537 );
538
539 //
540 //Program HDA PME_EN
541 //
542 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
543
544 //
545 //Program SATA PME_EN
546 //
547 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
548
549 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
550 if (mSystemConfiguration.EhciPllCfgEnable != 1) {
551 //
552 //Program EHCI PME_EN
553 //
554 PchMmPci32Or (
555 0,
556 0,
557 PCI_DEVICE_NUMBER_PCH_USB,
558 PCI_FUNCTION_NUMBER_PCH_EHCI,
559 R_PCH_EHCI_PWR_CNTL_STS,
560 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
561 );
562 }
563 {
564 UINTN EhciPciMmBase;
565 UINT32 Buffer32 = 0;
566
567 EhciPciMmBase = MmPciAddress (0,
568 0,
569 PCI_DEVICE_NUMBER_PCH_USB,
570 PCI_FUNCTION_NUMBER_PCH_EHCI,
571 0
572 );
573 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
574 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
575 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
576 }
577 }
578
579 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
580
581 #endif
582
583
584 EFI_STATUS
585 EFIAPI
586 TristateLpcGpioS0i3Config (
587 UINT32 Gpio_Mmio_Offset,
588 UINT32 Gpio_Pin_Num,
589 CFIO_PNP_INIT* Gpio_Conf_Data
590 )
591 {
592
593 UINT32 index;
594 UINT32 mmio_reg;
595 UINT32 mmio_val;
596
597 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
598
599 for(index=0; index < Gpio_Pin_Num; index++)
600 {
601 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
602
603 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
604 mmio_val = 0;
605 mmio_val = MmioRead32(mmio_reg);
606
607 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
608 }
609
610 return EFI_SUCCESS;
611 }
612
613
614 EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
615
616 /**
617 Event Notification during exit boot service to enabel ACPI mode
618
619 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
620
621 Clear all ACPI event status and disable all ACPI events
622 Disable PM sources except power button
623 Clear status bits
624
625 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
626
627 Update EC to disable SMI and enable SCI
628
629 Enable SCI
630
631 Enable PME_B0_EN in GPE0a_EN
632
633 @param Event - EFI Event Handle
634 @param Context - Pointer to Notify Context
635
636 @retval Nothing
637
638 **/
639 VOID
640 EFIAPI
641 EnableAcpiCallback (
642 IN EFI_EVENT Event,
643 IN VOID *Context
644 )
645 {
646 UINT32 RegData32;
647 UINT16 Pm1Cnt;
648 UINT16 AcpiBase;
649 UINT32 Gpe0aEn;
650
651 AcpiBase = MmioRead16 (
652 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
653 PCI_DEVICE_NUMBER_PCH_LPC,
654 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
655 ) & B_PCH_LPC_ACPI_BASE_BAR;
656
657 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
658
659 //
660 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
661 //
662 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
663 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
664 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
665
666 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
667 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
668 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
669
670 //
671 // Disable PM sources except power button
672 // power button is enabled only for PCAT. Disabled it on Tablet platform
673 //
674
675 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
676 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
677
678 //
679 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
680 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
681 //
682 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
683 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
684
685 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
686 RegData32 &= ~(BIT7);
687 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
688
689 //
690 // Enable SCI
691 //
692 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
693 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
694 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
695
696 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
697
698 //
699 // Enable PME_B0_EN in GPE0a_EN
700 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
701 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
702 //
703 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
704 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
705 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
706
707 }
708
709 /**
710
711 Routine Description:
712
713 This is the standard EFI driver point for the Driver. This
714 driver is responsible for setting up any platform specific policy or
715 initialization information.
716
717 @param ImageHandle Handle for the image of this driver.
718 @param SystemTable Pointer to the EFI System Table.
719
720 @retval EFI_SUCCESS Policy decisions set.
721
722 **/
723 EFI_STATUS
724 EFIAPI
725 InitializePlatform (
726 IN EFI_HANDLE ImageHandle,
727 IN EFI_SYSTEM_TABLE *SystemTable
728 )
729 {
730 EFI_STATUS Status;
731 UINTN VarSize;
732 EFI_HANDLE Handle = NULL;
733 EFI_EVENT mEfiExitBootServicesEvent;
734 EFI_EVENT RtcEvent;
735 VOID *RtcCallbackReg = NULL;
736
737 mImageHandle = ImageHandle;
738
739 Status = gBS->InstallProtocolInterface (
740 &Handle,
741 &gEfiSpeakerInterfaceProtocolGuid,
742 EFI_NATIVE_INTERFACE,
743 &mSpeakerInterface
744 );
745
746 Status = gBS->LocateProtocol (
747 &gEfiPciRootBridgeIoProtocolGuid,
748 NULL,
749 (VOID **) &mPciRootBridgeIo
750 );
751 ASSERT_EFI_ERROR (Status);
752
753 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
754 Status = gRT->GetVariable(
755 L"PlatformInfo",
756 &gEfiVlv2VariableGuid,
757 NULL,
758 &VarSize,
759 &mPlatformInfo
760 );
761
762 //
763 // Initialize Product Board ID variable
764 //
765 InitMfgAndConfigModeStateVar();
766 InitPlatformBootMode();
767
768 //
769 // Install Observable protocol
770 //
771 InitializeObservableProtocol();
772
773 Status = SaveSetupRecoveryVar();
774 if (EFI_ERROR (Status)) {
775 DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable failed \n"));
776 }
777
778 VarSize = sizeof(SYSTEM_CONFIGURATION);
779 Status = gRT->GetVariable(
780 NORMAL_SETUP_NAME,
781 &gEfiNormalSetupGuid,
782 NULL,
783 &VarSize,
784 &mSystemConfiguration
785 );
786 if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
787 //The setup variable is corrupted
788 VarSize = sizeof(SYSTEM_CONFIGURATION);
789 Status = gRT->GetVariable(
790 L"SetupRecovery",
791 &gEfiNormalSetupGuid,
792 NULL,
793 &VarSize,
794 &mSystemConfiguration
795 );
796 ASSERT_EFI_ERROR (Status);
797 Status = gRT->SetVariable (
798 NORMAL_SETUP_NAME,
799 &gEfiNormalSetupGuid,
800 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
801 sizeof(SYSTEM_CONFIGURATION),
802 &mSystemConfiguration
803 );
804 }
805
806 Status = EfiCreateEventReadyToBootEx (
807 TPL_CALLBACK,
808 ReadyToBootFunction,
809 NULL,
810 &mReadyToBootEvent
811 );
812
813 //
814 // Create a ReadyToBoot Event to run the PME init process
815 //
816 Status = EfiCreateEventReadyToBootEx (
817 TPL_CALLBACK,
818 InitPciDevPME,
819 NULL,
820 &mReadyToBootEvent
821 );
822 //
823 // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
824 //
825 if(mSystemConfiguration.SpiRwProtect==1) {
826 Status = EfiCreateEventReadyToBootEx (
827 TPL_CALLBACK,
828 SpiBiosProtectionFunction,
829 NULL,
830 &mReadyToBootEvent
831 );
832 }
833
834 ReportStatusCodeEx (
835 EFI_PROGRESS_CODE,
836 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
837 0,
838 &gEfiCallerIdGuid,
839 NULL,
840 NULL,
841 0
842 );
843
844 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
845 //
846 // Initialize Sensor Info variable
847 //
848 InitializeSensorInfoVariable();
849 #endif
850 InitPchPlatformPolicy(&mPlatformInfo);
851 InitVlvPlatformPolicy();
852
853 //
854 // Add usb policy
855 //
856 InitPlatformUsbPolicy();
857 InitSioPlatformPolicy();
858 InitializeClockRouting();
859 InitializeSlotInfo();
860 InitTcoReset();
861
862 //
863 //Init ExI
864 //
865 InitExI();
866
867 ReportStatusCodeEx (
868 EFI_PROGRESS_CODE,
869 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
870 0,
871 &gEfiCallerIdGuid,
872 NULL,
873 NULL,
874 0
875 );
876
877 //
878 // Install PCI Bus Driver Hook
879 //
880 PciBusDriverHook();
881
882 InitItk();
883
884 ReportStatusCodeEx (
885 EFI_PROGRESS_CODE,
886 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
887 0,
888 &gEfiCallerIdGuid,
889 NULL,
890 NULL,
891 0
892 );
893
894
895 //
896 // Initialize Password States and Callbacks
897 //
898 PchInitBeforeBoot();
899
900 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
901
902 #endif
903
904 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
905 //
906 // Re-write Firmware ID if it is changed
907 //
908 InitFirmwareId();
909 #endif
910
911 ReportStatusCodeEx (
912 EFI_PROGRESS_CODE,
913 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
914 0,
915 &gEfiCallerIdGuid,
916 NULL,
917 NULL,
918 0
919 );
920
921
922 Status = gBS->CreateEventEx (
923 EVT_NOTIFY_SIGNAL,
924 TPL_NOTIFY,
925 EnableAcpiCallback,
926 NULL,
927 &gEfiEventExitBootServicesGuid,
928 &mEfiExitBootServicesEvent
929 );
930
931 //
932 // Adjust RTC deafult time to be BIOS-built time.
933 //
934 Status = gBS->CreateEvent (
935 EVT_NOTIFY_SIGNAL,
936 TPL_CALLBACK,
937 AdjustDefaultRtcTimeCallback,
938 NULL,
939 &RtcEvent
940 );
941 if (!EFI_ERROR (Status)) {
942 Status = gBS->RegisterProtocolNotify (
943 &gExitPmAuthProtocolGuid,
944 RtcEvent,
945 &RtcCallbackReg
946 );
947
948 }
949
950 return EFI_SUCCESS;
951 }
952
953 /**
954 Source Or Destination with Length bytes.
955
956 @param[in] Destination Target memory
957 @param[in] Source Source memory
958 @param[in] Length Number of bytes
959
960 @retval None
961
962 **/
963 VOID
964 EfiOrMem (
965 IN VOID *Destination,
966 IN VOID *Source,
967 IN UINTN Length
968 )
969 {
970 CHAR8 *Destination8;
971 CHAR8 *Source8;
972
973 if (Source < Destination) {
974 Destination8 = (CHAR8 *) Destination + Length - 1;
975 Source8 = (CHAR8 *) Source + Length - 1;
976 while (Length--) {
977 *(Destination8--) |= *(Source8--);
978 }
979 } else {
980 Destination8 = (CHAR8 *) Destination;
981 Source8 = (CHAR8 *) Source;
982 while (Length--) {
983 *(Destination8++) |= *(Source8++);
984 }
985 }
986 }
987
988 VOID
989 PchInitBeforeBoot()
990 {
991 //
992 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
993 //
994 S3BootScriptSaveMemWrite (
995 EfiBootScriptWidthUint32,
996 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
997 1,
998 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
999
1000 S3BootScriptSaveMemWrite (
1001 EfiBootScriptWidthUint32,
1002 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
1003 1,
1004 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
1005
1006 S3BootScriptSaveMemWrite (
1007 EfiBootScriptWidthUint16,
1008 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
1009 1,
1010 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
1011
1012 S3BootScriptSaveMemWrite (
1013 EfiBootScriptWidthUint16,
1014 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
1015 1,
1016 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
1017
1018 //
1019 // Saved MTPMC_1 for S3 resume.
1020 //
1021 S3BootScriptSaveMemWrite (
1022 EfiBootScriptWidthUint32,
1023 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
1024 1,
1025 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
1026 return;
1027 }
1028
1029 VOID
1030 EFIAPI
1031 ReadyToBootFunction (
1032 EFI_EVENT Event,
1033 VOID *Context
1034 )
1035 {
1036 EFI_STATUS Status;
1037 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
1038 EFI_ISA_ACPI_DEVICE_ID IsaDevice;
1039 UINTN Size;
1040 UINT16 State;
1041 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
1042 EFI_CPU_IO_PROTOCOL *CpuIo;
1043 UINT8 Data;
1044 UINT8 ReceiveBuffer [64];
1045 UINT32 ReceiveBufferSize;
1046
1047 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
1048 0x00, 0x00, 0x00, 0x0A,
1049 0x00, 0x00, 0x00, 0x5D};
1050 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
1051 0x00, 0x00, 0x00, 0x0C,
1052 0x40, 0x00, 0x00, 0x0A,
1053 0x00, 0x00};
1054 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
1055 0x00, 0x00, 0x00, 0x0A,
1056 0x00, 0x00, 0x00, 0x70};
1057 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
1058 0x00, 0x00, 0x00, 0x0A,
1059 0x00, 0x00, 0x00, 0x6F};
1060 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
1061 0x00, 0x00, 0x00, 0x0B,
1062 0x00, 0x00, 0x00, 0x72,
1063 0x00};
1064 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
1065 0x00, 0x00, 0x00, 0x0B,
1066 0x00, 0x00, 0x00, 0x71,
1067 0x00};
1068
1069 Size = sizeof(UINT16);
1070 Status = gRT->GetVariable (
1071 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
1072 &gEfiNormalSetupGuid,
1073 NULL,
1074 &Size,
1075 &State
1076 );
1077
1078 //
1079 // Disable Floppy Controller if needed
1080 //
1081 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
1082 if (!EFI_ERROR(Status) && (State == 0x00)) {
1083 IsaDevice.HID = EISA_PNP_ID(0x604);
1084 IsaDevice.UID = 0;
1085 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
1086 }
1087
1088 //
1089 // save LAN info to a variable
1090 //
1091 if (NULL != mPciLanInfo) {
1092 gRT->SetVariable (
1093 L"PciLanInfo",
1094 &gEfiPciLanInfoGuid,
1095 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
1096 mPciLanCount * sizeof(PCI_LAN_INFO),
1097 mPciLanInfo
1098 );
1099 }
1100
1101 if (NULL != mPciLanInfo) {
1102 gBS->FreePool (mPciLanInfo);
1103 mPciLanInfo = NULL;
1104 }
1105
1106
1107 //
1108 // Handle ACPI OS TPM requests here
1109 //
1110 Status = gBS->LocateProtocol (
1111 &gEfiCpuIoProtocolGuid,
1112 NULL,
1113 (VOID **)&CpuIo
1114 );
1115 Status = gBS->LocateProtocol (
1116 &gEfiTpmMpDriverProtocolGuid,
1117 NULL,
1118 (VOID **)&TpmMpDriver
1119 );
1120 if (!EFI_ERROR (Status))
1121 {
1122 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
1123
1124 //
1125 // Clear pending ACPI TPM request indicator
1126 //
1127 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
1128 if (Data != 0)
1129 {
1130 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
1131
1132 //
1133 // Assert Physical Presence for these commands
1134 //
1135 TpmPhysicalPresenceCommand [11] = 0x20;
1136 ReceiveBufferSize = sizeof(ReceiveBuffer);
1137 Status = TpmMpDriver->Transmit (
1138 TpmMpDriver, TpmPhysicalPresenceCommand,
1139 sizeof (TpmPhysicalPresenceCommand),
1140 ReceiveBuffer, &ReceiveBufferSize
1141 );
1142 //
1143 // PF PhysicalPresence = TRUE
1144 //
1145 TpmPhysicalPresenceCommand [11] = 0x08;
1146 ReceiveBufferSize = sizeof(ReceiveBuffer);
1147 Status = TpmMpDriver->Transmit (
1148 TpmMpDriver, TpmPhysicalPresenceCommand,
1149 sizeof (TpmPhysicalPresenceCommand),
1150 ReceiveBuffer,
1151 &ReceiveBufferSize
1152 );
1153 if (Data == 0x01)
1154 {
1155 //
1156 // TPM_PhysicalEnable
1157 //
1158 ReceiveBufferSize = sizeof(ReceiveBuffer);
1159 Status = TpmMpDriver->Transmit (
1160 TpmMpDriver, TpmPhysicalEnableCommand,
1161 sizeof (TpmPhysicalEnableCommand),
1162 ReceiveBuffer, &ReceiveBufferSize
1163 );
1164 }
1165 if (Data == 0x02)
1166 {
1167 //
1168 // TPM_PhysicalDisable
1169 //
1170 ReceiveBufferSize = sizeof(ReceiveBuffer);
1171 Status = TpmMpDriver->Transmit (
1172 TpmMpDriver, TpmPhysicalDisableCommand,
1173 sizeof (TpmPhysicalDisableCommand),
1174 ReceiveBuffer,
1175 &ReceiveBufferSize
1176 );
1177 }
1178 if (Data == 0x03)
1179 {
1180 //
1181 // TPM_PhysicalSetDeactivated=FALSE
1182 //
1183 ReceiveBufferSize = sizeof(ReceiveBuffer);
1184 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1185 Status = TpmMpDriver->Transmit (
1186 TpmMpDriver,
1187 TpmPhysicalSetDeactivatedCommand,
1188 sizeof (TpmPhysicalSetDeactivatedCommand),
1189 ReceiveBuffer, &ReceiveBufferSize
1190 );
1191 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
1192 }
1193 if (Data == 0x04)
1194 {
1195 //
1196 // TPM_PhysicalSetDeactivated=TRUE
1197 //
1198 ReceiveBufferSize = sizeof(ReceiveBuffer);
1199 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1200 Status = TpmMpDriver->Transmit (
1201 TpmMpDriver,
1202 TpmPhysicalSetDeactivatedCommand,
1203 sizeof (TpmPhysicalSetDeactivatedCommand),
1204 ReceiveBuffer,
1205 &ReceiveBufferSize
1206 );
1207 gRT->ResetSystem (
1208 EfiResetWarm,
1209 EFI_SUCCESS,
1210 0,
1211 NULL
1212 );
1213 }
1214 if (Data == 0x05)
1215 {
1216 //
1217 // TPM_ForceClear
1218 //
1219 ReceiveBufferSize = sizeof(ReceiveBuffer);
1220 Status = TpmMpDriver->Transmit (
1221 TpmMpDriver,
1222 TpmForceClearCommand,
1223 sizeof (TpmForceClearCommand),
1224 ReceiveBuffer,
1225 &ReceiveBufferSize
1226 );
1227 gRT->ResetSystem (
1228 EfiResetWarm,
1229 EFI_SUCCESS,
1230 0,
1231 NULL
1232 );
1233 }
1234 if (Data == 0x06)
1235 {
1236 //
1237 // TPM_PhysicalEnable
1238 //
1239 ReceiveBufferSize = sizeof(ReceiveBuffer);
1240 Status = TpmMpDriver->Transmit (
1241 TpmMpDriver,
1242 TpmPhysicalEnableCommand,
1243 sizeof (TpmPhysicalEnableCommand),
1244 ReceiveBuffer,
1245 &ReceiveBufferSize
1246 );
1247 //
1248 // TPM_PhysicalSetDeactivated=FALSE
1249 //
1250 ReceiveBufferSize = sizeof(ReceiveBuffer);
1251 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1252 Status = TpmMpDriver->Transmit (
1253 TpmMpDriver,
1254 TpmPhysicalSetDeactivatedCommand,
1255 sizeof (TpmPhysicalSetDeactivatedCommand),
1256 ReceiveBuffer,
1257 &ReceiveBufferSize
1258 );
1259 gRT->ResetSystem (
1260 EfiResetWarm,
1261 EFI_SUCCESS,
1262 0,
1263 NULL
1264 );
1265 }
1266 if (Data == 0x07)
1267 {
1268 //
1269 // TPM_PhysicalSetDeactivated=TRUE
1270 //
1271 ReceiveBufferSize = sizeof(ReceiveBuffer);
1272 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1273 Status = TpmMpDriver->Transmit (
1274 TpmMpDriver,
1275 TpmPhysicalSetDeactivatedCommand,
1276 sizeof (TpmPhysicalSetDeactivatedCommand),
1277 ReceiveBuffer,
1278 &ReceiveBufferSize
1279 );
1280 //
1281 // TPM_PhysicalDisable
1282 //
1283 ReceiveBufferSize = sizeof(ReceiveBuffer);
1284 Status = TpmMpDriver->Transmit (
1285 TpmMpDriver,
1286 TpmPhysicalDisableCommand,
1287 sizeof (TpmPhysicalDisableCommand),
1288 ReceiveBuffer,
1289 &ReceiveBufferSize
1290 );
1291 gRT->ResetSystem (
1292 EfiResetWarm,
1293 EFI_SUCCESS,
1294 0,
1295 NULL
1296 );
1297 }
1298 if (Data == 0x08)
1299 {
1300 //
1301 // TPM_SetOwnerInstall=TRUE
1302 //
1303 ReceiveBufferSize = sizeof(ReceiveBuffer);
1304 TpmSetOwnerInstallCommand [10] = 0x01;
1305 Status = TpmMpDriver->Transmit (
1306 TpmMpDriver,
1307 TpmSetOwnerInstallCommand,
1308 sizeof (TpmSetOwnerInstallCommand),
1309 ReceiveBuffer,
1310 &ReceiveBufferSize
1311 );
1312 }
1313 if (Data == 0x09)
1314 {
1315 //
1316 // TPM_SetOwnerInstall=FALSE
1317 //
1318 ReceiveBufferSize = sizeof(ReceiveBuffer);
1319 TpmSetOwnerInstallCommand [10] = 0x00;
1320 Status = TpmMpDriver->Transmit (
1321 TpmMpDriver,
1322 TpmSetOwnerInstallCommand,
1323 sizeof (TpmSetOwnerInstallCommand),
1324 ReceiveBuffer,
1325 &ReceiveBufferSize
1326 );
1327 }
1328 if (Data == 0x0A)
1329 {
1330 //
1331 // TPM_PhysicalEnable
1332 //
1333 ReceiveBufferSize = sizeof(ReceiveBuffer);
1334 Status = TpmMpDriver->Transmit (
1335 TpmMpDriver,
1336 TpmPhysicalEnableCommand,
1337 sizeof (TpmPhysicalEnableCommand),
1338 ReceiveBuffer,
1339 &ReceiveBufferSize
1340 );
1341 //
1342 // TPM_PhysicalSetDeactivated=FALSE
1343 //
1344 ReceiveBufferSize = sizeof(ReceiveBuffer);
1345 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1346 Status = TpmMpDriver->Transmit (
1347 TpmMpDriver,
1348 TpmPhysicalSetDeactivatedCommand,
1349 sizeof (TpmPhysicalSetDeactivatedCommand),
1350 ReceiveBuffer,
1351 &ReceiveBufferSize
1352 );
1353 //
1354 // Do TPM_SetOwnerInstall=TRUE on next reboot
1355 //
1356
1357 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
1358
1359 gRT->ResetSystem (
1360 EfiResetWarm,
1361 EFI_SUCCESS,
1362 0,
1363 NULL
1364 );
1365 }
1366 if (Data == 0x0B)
1367 {
1368 //
1369 // TPM_SetOwnerInstall=FALSE
1370 //
1371 ReceiveBufferSize = sizeof(ReceiveBuffer);
1372 TpmSetOwnerInstallCommand [10] = 0x00;
1373 Status = TpmMpDriver->Transmit (
1374 TpmMpDriver,
1375 TpmSetOwnerInstallCommand,
1376 sizeof (TpmSetOwnerInstallCommand),
1377 ReceiveBuffer,
1378 &ReceiveBufferSize
1379 );
1380 //
1381 // TPM_PhysicalSetDeactivated=TRUE
1382 //
1383 ReceiveBufferSize = sizeof(ReceiveBuffer);
1384 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1385 Status = TpmMpDriver->Transmit (
1386 TpmMpDriver,
1387 TpmPhysicalSetDeactivatedCommand,
1388 sizeof (TpmPhysicalSetDeactivatedCommand),
1389 ReceiveBuffer,
1390 &ReceiveBufferSize
1391 );
1392 //
1393 // TPM_PhysicalDisable
1394 //
1395 ReceiveBufferSize = sizeof(ReceiveBuffer);
1396 Status = TpmMpDriver->Transmit (
1397 TpmMpDriver,
1398 TpmPhysicalDisableCommand,
1399 sizeof (TpmPhysicalDisableCommand),
1400 ReceiveBuffer,
1401 &ReceiveBufferSize
1402 );
1403 gRT->ResetSystem (
1404 EfiResetWarm,
1405 EFI_SUCCESS,
1406 0,
1407 NULL
1408 );
1409 }
1410 if (Data == 0x0E)
1411 {
1412 //
1413 // TPM_ForceClear
1414 //
1415 ReceiveBufferSize = sizeof(ReceiveBuffer);
1416 Status = TpmMpDriver->Transmit (
1417 TpmMpDriver,
1418 TpmForceClearCommand,
1419 sizeof (TpmForceClearCommand),
1420 ReceiveBuffer,
1421 &ReceiveBufferSize
1422 );
1423 //
1424 // TPM_PhysicalEnable
1425 //
1426 ReceiveBufferSize = sizeof(ReceiveBuffer);
1427 Status = TpmMpDriver->Transmit (
1428 TpmMpDriver,
1429 TpmPhysicalEnableCommand,
1430 sizeof (TpmPhysicalEnableCommand),
1431 ReceiveBuffer,
1432 &ReceiveBufferSize
1433 );
1434 //
1435 // TPM_PhysicalSetDeactivated=FALSE
1436 //
1437 ReceiveBufferSize = sizeof(ReceiveBuffer);
1438 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1439 Status = TpmMpDriver->Transmit (
1440 TpmMpDriver,
1441 TpmPhysicalSetDeactivatedCommand,
1442 sizeof (TpmPhysicalSetDeactivatedCommand),
1443 ReceiveBuffer,
1444 &ReceiveBufferSize
1445 );
1446 gRT->ResetSystem (
1447 EfiResetWarm,
1448 EFI_SUCCESS,
1449 0,
1450 NULL
1451 );
1452 }
1453 if (Data == 0xF0)
1454 {
1455 //
1456 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1457 //
1458 ReceiveBufferSize = sizeof(ReceiveBuffer);
1459 TpmSetOwnerInstallCommand [10] = 0x01;
1460 Status = TpmMpDriver->Transmit (
1461 TpmMpDriver,
1462 TpmSetOwnerInstallCommand,
1463 sizeof (TpmSetOwnerInstallCommand),
1464 ReceiveBuffer,
1465 &ReceiveBufferSize
1466 );
1467 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
1468 }
1469 //
1470 // Deassert Physical Presence
1471 //
1472 TpmPhysicalPresenceCommand [11] = 0x10;
1473 ReceiveBufferSize = sizeof(ReceiveBuffer);
1474 Status = TpmMpDriver->Transmit (
1475 TpmMpDriver,
1476 TpmPhysicalPresenceCommand,
1477 sizeof (TpmPhysicalPresenceCommand),
1478 ReceiveBuffer,
1479 &ReceiveBufferSize
1480 );
1481 }
1482 }
1483
1484 return;
1485 }
1486
1487 /**
1488
1489 Initializes manufacturing and config mode setting.
1490
1491 **/
1492 VOID
1493 InitMfgAndConfigModeStateVar()
1494 {
1495 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1496 VOID *HobList;
1497
1498
1499 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1500 if (HobList != NULL) {
1501 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1502
1503 //
1504 // Check if in Manufacturing mode
1505 //
1506 if ( !CompareMem (
1507 &BootModeBuffer->SetupName,
1508 MANUFACTURE_SETUP_NAME,
1509 StrSize (MANUFACTURE_SETUP_NAME)
1510 ) ) {
1511 mMfgMode = TRUE;
1512 }
1513
1514
1515
1516 }
1517
1518 }
1519
1520 /**
1521
1522 Initializes manufacturing and config mode setting.
1523
1524 **/
1525 VOID
1526 InitPlatformBootMode()
1527 {
1528 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1529 VOID *HobList;
1530
1531 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1532 if (HobList != NULL) {
1533 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1534 mPlatformBootMode = BootModeBuffer->PlatformBootMode;
1535 }
1536 }
1537
1538 /**
1539
1540 Initializes ITK.
1541
1542 **/
1543 VOID
1544 InitItk(
1545 )
1546 {
1547 EFI_STATUS Status;
1548 UINT16 ItkModBiosState;
1549 UINT8 Value;
1550 UINTN DataSize;
1551 UINT32 Attributes;
1552
1553 //
1554 // Setup local variable according to ITK variable
1555 //
1556 //
1557 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1558 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1559 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1560 //
1561 DataSize = sizeof (Value);
1562 Status = gRT->GetVariable (
1563 ITK_BIOS_MOD_VAR_NAME,
1564 &gItkDataVarGuid,
1565 &Attributes,
1566 &DataSize,
1567 &Value
1568 );
1569 if (Status == EFI_NOT_FOUND) {
1570 //
1571 // Variable not found, hasn't been initialized, intialize to 0
1572 //
1573 Value=0x00;
1574 //
1575 // Write variable to flash.
1576 //
1577 gRT->SetVariable (
1578 ITK_BIOS_MOD_VAR_NAME,
1579 &gItkDataVarGuid,
1580 EFI_VARIABLE_RUNTIME_ACCESS |
1581 EFI_VARIABLE_NON_VOLATILE |
1582 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1583 sizeof (Value),
1584 &Value
1585 );
1586
1587 }
1588 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
1589 if (Value == 0x00) {
1590 ItkModBiosState = 0x00;
1591 } else {
1592 ItkModBiosState = 0x01;
1593 }
1594 gRT->SetVariable (
1595 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
1596 &gEfiNormalSetupGuid,
1597 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1598 2,
1599 (void *)&ItkModBiosState
1600 );
1601 }
1602 }
1603
1604 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1605
1606 /**
1607
1608 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1609
1610 **/
1611 STATIC
1612 VOID
1613 InitFirmwareId(
1614 )
1615 {
1616 EFI_STATUS Status;
1617 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
1618
1619 //
1620 // First try writing the variable without a password in case we are
1621 // upgrading from a BIOS without password protection on the FirmwareId
1622 //
1623 Status = gRT->SetVariable(
1624 (CHAR16 *)&gFirmwareIdName,
1625 &gFirmwareIdGuid,
1626 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1627 EFI_VARIABLE_RUNTIME_ACCESS,
1628 sizeof( FIRMWARE_ID ) - 1,
1629 FIRMWARE_ID
1630 );
1631
1632 if (Status == EFI_INVALID_PARAMETER) {
1633
1634 //
1635 // Since setting the firmware id without the password failed,
1636 // a password must be required.
1637 //
1638 Status = gRT->SetVariable(
1639 (CHAR16 *)&FirmwareIdNameWithPassword,
1640 &gFirmwareIdGuid,
1641 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1642 EFI_VARIABLE_RUNTIME_ACCESS,
1643 sizeof( FIRMWARE_ID ) - 1,
1644 FIRMWARE_ID
1645 );
1646 }
1647 }
1648 #endif
1649
1650 VOID
1651 UpdateDVMTSetup(
1652 )
1653 {
1654 //
1655 // Workaround to support IIA bug.
1656 // IIA request to change option value to 4, 5 and 7 relatively
1657 // instead of 1, 2, and 3 which follow Lakeport Specs.
1658 // Check option value, temporary hardcode GraphicsDriverMemorySize
1659 // Option value to fulfill IIA requirment. So that user no need to
1660 // load default and update setupvariable after update BIOS.
1661 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1662 // *This is for broadwater and above product only.
1663 //
1664
1665 SYSTEM_CONFIGURATION SystemConfiguration;
1666 UINTN VarSize;
1667 EFI_STATUS Status;
1668
1669 VarSize = sizeof(SYSTEM_CONFIGURATION);
1670 Status = gRT->GetVariable(
1671 NORMAL_SETUP_NAME,
1672 &gEfiNormalSetupGuid,
1673 NULL,
1674 &VarSize,
1675 &SystemConfiguration
1676 );
1677
1678 if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
1679 //The setup variable is corrupted
1680 VarSize = sizeof(SYSTEM_CONFIGURATION);
1681 Status = gRT->GetVariable(
1682 L"SetupRecovery",
1683 &gEfiNormalSetupGuid,
1684 NULL,
1685 &VarSize,
1686 &SystemConfiguration
1687 );
1688 ASSERT_EFI_ERROR (Status);
1689 }
1690
1691 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
1692 switch (SystemConfiguration.GraphicsDriverMemorySize){
1693 case 1:
1694 SystemConfiguration.GraphicsDriverMemorySize = 4;
1695 break;
1696 case 2:
1697 SystemConfiguration.GraphicsDriverMemorySize = 5;
1698 break;
1699 case 3:
1700 SystemConfiguration.GraphicsDriverMemorySize = 7;
1701 break;
1702 default:
1703 break;
1704 }
1705
1706 Status = gRT->SetVariable (
1707 NORMAL_SETUP_NAME,
1708 &gEfiNormalSetupGuid,
1709 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
1710 sizeof(SYSTEM_CONFIGURATION),
1711 &SystemConfiguration
1712 );
1713 }
1714 }
1715
1716 VOID
1717 InitPlatformUsbPolicy (
1718 VOID
1719 )
1720
1721 {
1722 EFI_HANDLE Handle;
1723 EFI_STATUS Status;
1724
1725 Handle = NULL;
1726
1727 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
1728 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
1729 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
1730 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
1731 } else {
1732 mUsbPolicyData.UsbEmulationSize = 0;
1733 }
1734 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
1735 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
1736
1737 //
1738 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1739 //
1740 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
1741
1742 //
1743 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1744 //
1745 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
1746
1747 //
1748 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1749 //
1750 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
1751
1752 //
1753 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1754 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1755 mUsbPolicyData.LpcAcpiBase = 0x40;
1756 mUsbPolicyData.AcpiTimerReg = 0x08;
1757
1758 //
1759 // Set for reduce usb post time
1760 //
1761 mUsbPolicyData.UsbTimeTue = 0x00;
1762 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
1763 mUsbPolicyData.EnumWaitPortStableStall = 100;
1764
1765
1766 Status = gBS->InstallProtocolInterface (
1767 &Handle,
1768 &gUsbPolicyGuid,
1769 EFI_NATIVE_INTERFACE,
1770 &mUsbPolicyData
1771 );
1772 ASSERT_EFI_ERROR(Status);
1773
1774 }
1775
1776 UINT8
1777 ReadCmosBank1Byte (
1778 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1779 IN UINT8 Index
1780 )
1781 {
1782 UINT8 Data;
1783
1784 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
1785 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
1786 return Data;
1787 }
1788
1789 VOID
1790 WriteCmosBank1Byte (
1791 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1792 IN UINT8 Index,
1793 IN UINT8 Data
1794 )
1795 {
1796 CpuIo->Io.Write (
1797 CpuIo,
1798 EfiCpuIoWidthUint8,
1799 0x72,
1800 1,
1801 &Index
1802 );
1803 CpuIo->Io.Write (
1804 CpuIo,
1805 EfiCpuIoWidthUint8,
1806 0x73,
1807 1,
1808 &Data
1809 );
1810 }
1811
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