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1 /** @file
2
3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
4
5
6 This program and the accompanying materials are licensed and made available under
7
8 the terms and conditions of the BSD License that accompanies this distribution.
9
10 The full text of the license may be found at
11
12 http://opensource.org/licenses/bsd-license.php.
13
14
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23 Module Name:
24
25
26 Platform.c
27
28 Abstract:
29
30 Platform Initialization Driver.
31
32
33 --*/
34
35 #include "PlatformDxe.h"
36 #include "Platform.h"
37 #include "PchCommonDefinitions.h"
38 #include <Protocol/UsbPolicy.h>
39 #include <Protocol/PchPlatformPolicy.h>
40 #include <Protocol/TpmMp.h>
41 #include <Protocol/CpuIo2.h>
42 #include <Library/S3BootScriptLib.h>
43 #include <Guid/PciLanInfo.h>
44 #include <Guid/ItkData.h>
45 #include <Library/PciLib.h>
46 #include <PlatformBootMode.h>
47 #include <Guid/EventGroup.h>
48 #include <Guid/Vlv2Variable.h>
49 #include <Protocol/GlobalNvsArea.h>
50 #include <Protocol/IgdOpRegion.h>
51 #include <Library/PcdLib.h>
52
53 //
54 // VLV2 GPIO GROUP OFFSET
55 //
56 #define GPIO_SCORE_OFFSET 0x0000
57 #define GPIO_NCORE_OFFSET 0x1000
58 #define GPIO_SSUS_OFFSET 0x2000
59
60 typedef struct {
61 UINT32 offset;
62 UINT32 val;
63 } CFIO_PNP_INIT;
64
65 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
66 {
67 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
68 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
69 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
70 };
71
72
73 EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
74 EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
75 SYSTEM_CONFIGURATION mSystemConfiguration;
76 SYSTEM_PASSWORDS mSystemPassword;
77 EFI_HANDLE mImageHandle;
78 BOOLEAN mMfgMode = FALSE;
79 VOID *mDxePlatformStringPack;
80 UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
81 extern CHAR16 gItkDataVarName[];
82
83
84 EFI_PLATFORM_INFO_HOB mPlatformInfo;
85 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
86 EFI_EVENT mReadyToBootEvent;
87
88 UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
89 UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
90 UINT32 mSubsystemVidDid;
91 UINT32 mSubsystemAudioVidDid;
92
93 UINTN mPciLanCount = 0;
94 VOID *mPciLanInfo = NULL;
95 UINTN SpiBase;
96
97 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
98 ProgramToneFrequency,
99 GenerateBeepTone
100 };
101
102 EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
103
104
105 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
106 {
107 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
108 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
109 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
110 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
111 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
112 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
113 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
114 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
115 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
116 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
117 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
118 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
119 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
120 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
121 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
122 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
123 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
124 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
125 };
126
127 VOID
128 EfiOrMem (
129 IN VOID *Destination,
130 IN VOID *Source,
131 IN UINTN Length
132 );
133
134 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
135 STATIC
136 VOID
137 InitFirmwareId();
138 #endif
139
140
141 VOID
142 InitializeClockRouting(
143 );
144
145 VOID
146 InitializeSlotInfo (
147 );
148
149 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
150 VOID
151 InitializeSensorInfoVariable (
152 );
153 #endif
154
155 VOID
156 InitTcoReset (
157 );
158
159 VOID
160 InitExI ();
161
162 VOID
163 InitItk();
164
165 VOID
166 InitPlatformBootMode();
167
168 VOID
169 InitMfgAndConfigModeStateVar();
170
171 VOID
172 InitPchPlatformPolicy (
173 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
174 );
175
176 VOID
177 InitVlvPlatformPolicy (
178 );
179
180 VOID
181 InitSioPlatformPolicy(
182 );
183
184 VOID
185 PchInitBeforeBoot(
186 );
187
188 VOID
189 UpdateDVMTSetup(
190 );
191
192 VOID
193 InitPlatformUsbPolicy (
194 VOID
195 );
196
197 VOID
198 InitRC6Policy(
199 VOID
200 );
201
202
203 VOID
204 TristateLpcGpioConfig (
205 IN UINT32 Gpio_Mmio_Offset,
206 IN UINT32 Gpio_Pin_Num,
207 GPIO_CONF_PAD_INIT* Gpio_Conf_Data
208 )
209
210 {
211 UINT32 index;
212 UINT32 mmio_conf0;
213 UINT32 mmio_padval;
214 PAD_CONF0 conf0_val;
215 PAD_VAL pad_val;
216
217 //
218 // GPIO WELL -- Memory base registers
219 //
220
221 //
222 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
223 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
224 //
225
226 for(index=0; index < Gpio_Pin_Num; index++)
227 {
228 //
229 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
230 //
231 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
232 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
233
234 #ifdef EFI_DEBUG
235 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
236
237 #endif
238 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
239 Gpio_Conf_Data[index].usage,
240 Gpio_Conf_Data[index].func,
241 Gpio_Conf_Data[index].int_type,
242 Gpio_Conf_Data[index].pull,
243 mmio_conf0));
244
245 //
246 // Step 1: PadVal Programming
247 //
248 pad_val.dw = MmioRead32(mmio_padval);
249
250 //
251 // Config PAD_VAL only for GPIO (Non-Native) Pin
252 //
253 if(Native != Gpio_Conf_Data[index].usage)
254 {
255 pad_val.dw &= ~0x6; // Clear bits 1:2
256 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
257
258 //
259 // set GPO default value
260 //
261 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
262 {
263 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
264 }
265 }
266
267
268 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
269
270 MmioWrite32(mmio_padval, pad_val.dw);
271
272 //
273 // Step 2: CONF0 Programming
274 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
275 //
276 conf0_val.dw = MmioRead32(mmio_conf0);
277
278 //
279 // Set Function #
280 //
281 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
282
283 if(GPO == Gpio_Conf_Data[index].usage)
284 {
285 //
286 // If used as GPO, then internal pull need to be disabled
287 //
288 conf0_val.r.Pull_assign = 0; // Non-pull
289 }
290 else
291 {
292 //
293 // Set PullUp / PullDown
294 //
295 if(P_20K_H == Gpio_Conf_Data[index].pull)
296 {
297 conf0_val.r.Pull_assign = 0x1; // PullUp
298 conf0_val.r.Pull_strength = 0x2;// 20K
299 }
300 else if(P_20K_L == Gpio_Conf_Data[index].pull)
301 {
302 conf0_val.r.Pull_assign = 0x2; // PullDown
303 conf0_val.r.Pull_strength = 0x2;// 20K
304 }
305 else if(P_NONE == Gpio_Conf_Data[index].pull)
306 {
307 conf0_val.r.Pull_assign = 0; // Non-pull
308 }
309 else
310 {
311 ASSERT(FALSE); // Invalid value
312 }
313 }
314
315 //
316 // Set INT Trigger Type
317 //
318 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
319
320 //
321 // Set INT Trigger Type
322 //
323 if(TRIG_ == Gpio_Conf_Data[index].int_type)
324 {
325 //
326 // Interrupt not capable, clear bits 27:24
327 //
328 }
329 else
330 {
331 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
332 }
333
334 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
335
336 //
337 // Write back the targeted GPIO config value according to platform (board) GPIO setting
338 //
339 MmioWrite32 (mmio_conf0, conf0_val.dw);
340 }
341
342 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
343 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
344 //
345 }
346
347 VOID
348 EFIAPI
349 SpiBiosProtectionFunction(
350 EFI_EVENT Event,
351 VOID *Context
352 )
353 {
354
355 UINTN mPciD31F0RegBase;
356 UINTN BiosFlaLower0;
357 UINTN BiosFlaLimit0;
358 UINTN BiosFlaLower1;
359 UINTN BiosFlaLimit1;
360
361
362 BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
363 BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
364 #ifdef MINNOW2_FSP_BUILD
365 BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);
366 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
367 #else
368 BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
369 BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
370 #endif
371
372
373 mPciD31F0RegBase = MmPciAddress (0,
374 DEFAULT_PCI_BUS_NUMBER_PCH,
375 PCI_DEVICE_NUMBER_PCH_LPC,
376 PCI_FUNCTION_NUMBER_PCH_LPC,
377 0
378 );
379 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
380
381 //
382 //Set SMM_BWP, WPD and LE bit
383 //
384 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
385 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
386 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
387
388 //
389 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
390 //
391 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
392 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
393 //
394 //Already locked. we could take no action here
395 //
396 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
397 return;
398 }
399
400 //
401 //Set PR0
402 //
403 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
404 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
405 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
406
407 //
408 //Lock down PR0
409 //
410 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
411
412 //
413 // Verify if it's really locked.
414 //
415 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
416 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
417 }
418
419 //
420 //Set PR1
421 //
422
423 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
424 B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
425 (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
426
427 //
428 //Lock down PR1
429 //
430 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
431
432 //
433 // Verify if it's really locked.
434 //
435 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
436 DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));
437 }
438 return;
439
440 }
441
442 VOID
443 EFIAPI
444 InitPciDevPME (
445 EFI_EVENT Event,
446 VOID *Context
447 )
448 {
449 UINTN VarSize;
450 EFI_STATUS Status;
451
452 VarSize = sizeof(SYSTEM_CONFIGURATION);
453 Status = gRT->GetVariable(
454 NORMAL_SETUP_NAME,
455 &gEfiNormalSetupGuid,
456 NULL,
457 &VarSize,
458 &mSystemConfiguration
459 );
460
461 //
462 //Program HDA PME_EN
463 //
464 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
465
466 //
467 //Program SATA PME_EN
468 //
469 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
470
471 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
472 if (mSystemConfiguration.EhciPllCfgEnable != 1) {
473 //
474 //Program EHCI PME_EN
475 //
476 PchMmPci32Or (
477 0,
478 0,
479 PCI_DEVICE_NUMBER_PCH_USB,
480 PCI_FUNCTION_NUMBER_PCH_EHCI,
481 R_PCH_EHCI_PWR_CNTL_STS,
482 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
483 );
484 }
485 {
486 UINTN EhciPciMmBase;
487 UINT32 Buffer32 = 0;
488
489 EhciPciMmBase = MmPciAddress (0,
490 0,
491 PCI_DEVICE_NUMBER_PCH_USB,
492 PCI_FUNCTION_NUMBER_PCH_EHCI,
493 0
494 );
495 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
496 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
497 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
498 }
499 }
500
501 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
502
503 #endif
504
505
506 EFI_STATUS
507 EFIAPI
508 TristateLpcGpioS0i3Config (
509 UINT32 Gpio_Mmio_Offset,
510 UINT32 Gpio_Pin_Num,
511 CFIO_PNP_INIT* Gpio_Conf_Data
512 )
513 {
514
515 UINT32 index;
516 UINT32 mmio_reg;
517 UINT32 mmio_val;
518
519 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
520
521 for(index=0; index < Gpio_Pin_Num; index++)
522 {
523 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
524
525 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
526 mmio_val = 0;
527 mmio_val = MmioRead32(mmio_reg);
528
529 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
530 }
531
532 return EFI_SUCCESS;
533 }
534
535
536 EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
537
538 /**
539 Event Notification during exit boot service to enabel ACPI mode
540
541 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
542
543 Clear all ACPI event status and disable all ACPI events
544 Disable PM sources except power button
545 Clear status bits
546
547 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
548
549 Update EC to disable SMI and enable SCI
550
551 Enable SCI
552
553 Enable PME_B0_EN in GPE0a_EN
554
555 @param Event - EFI Event Handle
556 @param Context - Pointer to Notify Context
557
558 @retval Nothing
559
560 **/
561 VOID
562 EFIAPI
563 EnableAcpiCallback (
564 IN EFI_EVENT Event,
565 IN VOID *Context
566 )
567 {
568 UINT32 RegData32;
569 UINT16 Pm1Cnt;
570 UINT16 AcpiBase;
571 UINT32 Gpe0aEn;
572
573 AcpiBase = MmioRead16 (
574 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
575 PCI_DEVICE_NUMBER_PCH_LPC,
576 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
577 ) & B_PCH_LPC_ACPI_BASE_BAR;
578
579 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
580
581 //
582 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
583 //
584 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
585 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
586 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
587
588 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
589 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
590 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
591
592 //
593 // Disable PM sources except power button
594 // power button is enabled only for PCAT. Disabled it on Tablet platform
595 //
596
597 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
598 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
599
600 //
601 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
602 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
603 //
604 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
605 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
606
607 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
608 RegData32 &= ~(BIT7);
609 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
610
611 //
612 // Enable SCI
613 //
614 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
615 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
616 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
617
618 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
619
620 //
621 // Enable PME_B0_EN in GPE0a_EN
622 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
623 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
624 //
625 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
626 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
627 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
628
629 }
630
631 /**
632
633 Routine Description:
634
635 This is the standard EFI driver point for the Driver. This
636 driver is responsible for setting up any platform specific policy or
637 initialization information.
638
639 @param ImageHandle Handle for the image of this driver.
640 @param SystemTable Pointer to the EFI System Table.
641
642 @retval EFI_SUCCESS Policy decisions set.
643
644 **/
645 EFI_STATUS
646 EFIAPI
647 InitializePlatform (
648 IN EFI_HANDLE ImageHandle,
649 IN EFI_SYSTEM_TABLE *SystemTable
650 )
651 {
652 EFI_STATUS Status;
653 UINTN VarSize;
654 EFI_HANDLE Handle = NULL;
655 EFI_EVENT mEfiExitBootServicesEvent;
656 EFI_EVENT RtcEvent;
657 VOID *RtcCallbackReg = NULL;
658
659 mImageHandle = ImageHandle;
660
661 Status = gBS->InstallProtocolInterface (
662 &Handle,
663 &gEfiSpeakerInterfaceProtocolGuid,
664 EFI_NATIVE_INTERFACE,
665 &mSpeakerInterface
666 );
667
668 Status = gBS->LocateProtocol (
669 &gEfiPciRootBridgeIoProtocolGuid,
670 NULL,
671 (VOID **) &mPciRootBridgeIo
672 );
673 ASSERT_EFI_ERROR (Status);
674
675 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
676 Status = gRT->GetVariable(
677 L"PlatformInfo",
678 &gEfiVlv2VariableGuid,
679 NULL,
680 &VarSize,
681 &mPlatformInfo
682 );
683
684 //
685 // Initialize Product Board ID variable
686 //
687 InitMfgAndConfigModeStateVar();
688 InitPlatformBootMode();
689
690 //
691 // Install Observable protocol
692 //
693 InitializeObservableProtocol();
694
695
696 VarSize = sizeof(SYSTEM_CONFIGURATION);
697 Status = gRT->GetVariable(
698 NORMAL_SETUP_NAME,
699 &gEfiNormalSetupGuid,
700 NULL,
701 &VarSize,
702 &mSystemConfiguration
703 );
704
705
706 Status = EfiCreateEventReadyToBootEx (
707 TPL_CALLBACK,
708 ReadyToBootFunction,
709 NULL,
710 &mReadyToBootEvent
711 );
712
713 //
714 // Create a ReadyToBoot Event to run the PME init process
715 //
716 Status = EfiCreateEventReadyToBootEx (
717 TPL_CALLBACK,
718 InitPciDevPME,
719 NULL,
720 &mReadyToBootEvent
721 );
722 //
723 // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
724 //
725 if(mSystemConfiguration.SpiRwProtect==1) {
726 Status = EfiCreateEventReadyToBootEx (
727 TPL_CALLBACK,
728 SpiBiosProtectionFunction,
729 NULL,
730 &mReadyToBootEvent
731 );
732 }
733
734 ReportStatusCodeEx (
735 EFI_PROGRESS_CODE,
736 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
737 0,
738 &gEfiCallerIdGuid,
739 NULL,
740 NULL,
741 0
742 );
743
744 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
745 //
746 // Initialize Sensor Info variable
747 //
748 InitializeSensorInfoVariable();
749 #endif
750 InitPchPlatformPolicy(&mPlatformInfo);
751 InitVlvPlatformPolicy();
752
753 //
754 // Add usb policy
755 //
756 InitPlatformUsbPolicy();
757 InitSioPlatformPolicy();
758 InitializeClockRouting();
759 InitializeSlotInfo();
760 InitTcoReset();
761
762 //
763 //Init ExI
764 //
765 InitExI();
766
767 ReportStatusCodeEx (
768 EFI_PROGRESS_CODE,
769 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
770 0,
771 &gEfiCallerIdGuid,
772 NULL,
773 NULL,
774 0
775 );
776
777 //
778 // Install PCI Bus Driver Hook
779 //
780 PciBusDriverHook();
781
782 InitItk();
783
784 ReportStatusCodeEx (
785 EFI_PROGRESS_CODE,
786 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
787 0,
788 &gEfiCallerIdGuid,
789 NULL,
790 NULL,
791 0
792 );
793
794
795 //
796 // Initialize Password States and Callbacks
797 //
798 PchInitBeforeBoot();
799
800 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
801
802 #endif
803
804 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
805 //
806 // Re-write Firmware ID if it is changed
807 //
808 InitFirmwareId();
809 #endif
810
811 ReportStatusCodeEx (
812 EFI_PROGRESS_CODE,
813 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
814 0,
815 &gEfiCallerIdGuid,
816 NULL,
817 NULL,
818 0
819 );
820
821
822 Status = gBS->CreateEventEx (
823 EVT_NOTIFY_SIGNAL,
824 TPL_NOTIFY,
825 EnableAcpiCallback,
826 NULL,
827 &gEfiEventExitBootServicesGuid,
828 &mEfiExitBootServicesEvent
829 );
830
831 //
832 // Adjust RTC deafult time to be BIOS-built time.
833 //
834 Status = gBS->CreateEvent (
835 EVT_NOTIFY_SIGNAL,
836 TPL_CALLBACK,
837 AdjustDefaultRtcTimeCallback,
838 NULL,
839 &RtcEvent
840 );
841 if (!EFI_ERROR (Status)) {
842 Status = gBS->RegisterProtocolNotify (
843 &gExitPmAuthProtocolGuid,
844 RtcEvent,
845 &RtcCallbackReg
846 );
847
848 }
849
850 return EFI_SUCCESS;
851 }
852
853 /**
854 Source Or Destination with Length bytes.
855
856 @param[in] Destination Target memory
857 @param[in] Source Source memory
858 @param[in] Length Number of bytes
859
860 @retval None
861
862 **/
863 VOID
864 EfiOrMem (
865 IN VOID *Destination,
866 IN VOID *Source,
867 IN UINTN Length
868 )
869 {
870 CHAR8 *Destination8;
871 CHAR8 *Source8;
872
873 if (Source < Destination) {
874 Destination8 = (CHAR8 *) Destination + Length - 1;
875 Source8 = (CHAR8 *) Source + Length - 1;
876 while (Length--) {
877 *(Destination8--) |= *(Source8--);
878 }
879 } else {
880 Destination8 = (CHAR8 *) Destination;
881 Source8 = (CHAR8 *) Source;
882 while (Length--) {
883 *(Destination8++) |= *(Source8++);
884 }
885 }
886 }
887
888 VOID
889 PchInitBeforeBoot()
890 {
891 //
892 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
893 //
894 S3BootScriptSaveMemWrite (
895 EfiBootScriptWidthUint32,
896 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
897 1,
898 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
899
900 S3BootScriptSaveMemWrite (
901 EfiBootScriptWidthUint32,
902 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
903 1,
904 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
905
906 S3BootScriptSaveMemWrite (
907 EfiBootScriptWidthUint16,
908 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
909 1,
910 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
911
912 S3BootScriptSaveMemWrite (
913 EfiBootScriptWidthUint16,
914 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
915 1,
916 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
917
918 //
919 // Saved MTPMC_1 for S3 resume.
920 //
921 S3BootScriptSaveMemWrite (
922 EfiBootScriptWidthUint32,
923 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
924 1,
925 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
926 return;
927 }
928
929 VOID
930 EFIAPI
931 ReadyToBootFunction (
932 EFI_EVENT Event,
933 VOID *Context
934 )
935 {
936 EFI_STATUS Status;
937 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
938 EFI_ISA_ACPI_DEVICE_ID IsaDevice;
939 UINTN Size;
940 UINT16 State;
941 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
942 EFI_CPU_IO_PROTOCOL *CpuIo;
943 UINT8 Data;
944 UINT8 ReceiveBuffer [64];
945 UINT32 ReceiveBufferSize;
946
947 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
948 0x00, 0x00, 0x00, 0x0A,
949 0x00, 0x00, 0x00, 0x5D};
950 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
951 0x00, 0x00, 0x00, 0x0C,
952 0x40, 0x00, 0x00, 0x0A,
953 0x00, 0x00};
954 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
955 0x00, 0x00, 0x00, 0x0A,
956 0x00, 0x00, 0x00, 0x70};
957 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
958 0x00, 0x00, 0x00, 0x0A,
959 0x00, 0x00, 0x00, 0x6F};
960 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
961 0x00, 0x00, 0x00, 0x0B,
962 0x00, 0x00, 0x00, 0x72,
963 0x00};
964 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
965 0x00, 0x00, 0x00, 0x0B,
966 0x00, 0x00, 0x00, 0x71,
967 0x00};
968
969 Size = sizeof(UINT16);
970 Status = gRT->GetVariable (
971 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
972 &gEfiNormalSetupGuid,
973 NULL,
974 &Size,
975 &State
976 );
977
978 //
979 // Disable Floppy Controller if needed
980 //
981 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
982 if (!EFI_ERROR(Status) && (State == 0x00)) {
983 IsaDevice.HID = EISA_PNP_ID(0x604);
984 IsaDevice.UID = 0;
985 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
986 }
987
988 //
989 // save LAN info to a variable
990 //
991 if (NULL != mPciLanInfo) {
992 gRT->SetVariable (
993 L"PciLanInfo",
994 &gEfiPciLanInfoGuid,
995 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
996 mPciLanCount * sizeof(PCI_LAN_INFO),
997 mPciLanInfo
998 );
999 }
1000
1001 if (NULL != mPciLanInfo) {
1002 gBS->FreePool (mPciLanInfo);
1003 mPciLanInfo = NULL;
1004 }
1005
1006
1007 //
1008 // Handle ACPI OS TPM requests here
1009 //
1010 Status = gBS->LocateProtocol (
1011 &gEfiCpuIoProtocolGuid,
1012 NULL,
1013 (VOID **)&CpuIo
1014 );
1015 Status = gBS->LocateProtocol (
1016 &gEfiTpmMpDriverProtocolGuid,
1017 NULL,
1018 (VOID **)&TpmMpDriver
1019 );
1020 if (!EFI_ERROR (Status))
1021 {
1022 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
1023
1024 //
1025 // Clear pending ACPI TPM request indicator
1026 //
1027 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
1028 if (Data != 0)
1029 {
1030 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
1031
1032 //
1033 // Assert Physical Presence for these commands
1034 //
1035 TpmPhysicalPresenceCommand [11] = 0x20;
1036 ReceiveBufferSize = sizeof(ReceiveBuffer);
1037 Status = TpmMpDriver->Transmit (
1038 TpmMpDriver, TpmPhysicalPresenceCommand,
1039 sizeof (TpmPhysicalPresenceCommand),
1040 ReceiveBuffer, &ReceiveBufferSize
1041 );
1042 //
1043 // PF PhysicalPresence = TRUE
1044 //
1045 TpmPhysicalPresenceCommand [11] = 0x08;
1046 ReceiveBufferSize = sizeof(ReceiveBuffer);
1047 Status = TpmMpDriver->Transmit (
1048 TpmMpDriver, TpmPhysicalPresenceCommand,
1049 sizeof (TpmPhysicalPresenceCommand),
1050 ReceiveBuffer,
1051 &ReceiveBufferSize
1052 );
1053 if (Data == 0x01)
1054 {
1055 //
1056 // TPM_PhysicalEnable
1057 //
1058 ReceiveBufferSize = sizeof(ReceiveBuffer);
1059 Status = TpmMpDriver->Transmit (
1060 TpmMpDriver, TpmPhysicalEnableCommand,
1061 sizeof (TpmPhysicalEnableCommand),
1062 ReceiveBuffer, &ReceiveBufferSize
1063 );
1064 }
1065 if (Data == 0x02)
1066 {
1067 //
1068 // TPM_PhysicalDisable
1069 //
1070 ReceiveBufferSize = sizeof(ReceiveBuffer);
1071 Status = TpmMpDriver->Transmit (
1072 TpmMpDriver, TpmPhysicalDisableCommand,
1073 sizeof (TpmPhysicalDisableCommand),
1074 ReceiveBuffer,
1075 &ReceiveBufferSize
1076 );
1077 }
1078 if (Data == 0x03)
1079 {
1080 //
1081 // TPM_PhysicalSetDeactivated=FALSE
1082 //
1083 ReceiveBufferSize = sizeof(ReceiveBuffer);
1084 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1085 Status = TpmMpDriver->Transmit (
1086 TpmMpDriver,
1087 TpmPhysicalSetDeactivatedCommand,
1088 sizeof (TpmPhysicalSetDeactivatedCommand),
1089 ReceiveBuffer, &ReceiveBufferSize
1090 );
1091 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
1092 }
1093 if (Data == 0x04)
1094 {
1095 //
1096 // TPM_PhysicalSetDeactivated=TRUE
1097 //
1098 ReceiveBufferSize = sizeof(ReceiveBuffer);
1099 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1100 Status = TpmMpDriver->Transmit (
1101 TpmMpDriver,
1102 TpmPhysicalSetDeactivatedCommand,
1103 sizeof (TpmPhysicalSetDeactivatedCommand),
1104 ReceiveBuffer,
1105 &ReceiveBufferSize
1106 );
1107 gRT->ResetSystem (
1108 EfiResetWarm,
1109 EFI_SUCCESS,
1110 0,
1111 NULL
1112 );
1113 }
1114 if (Data == 0x05)
1115 {
1116 //
1117 // TPM_ForceClear
1118 //
1119 ReceiveBufferSize = sizeof(ReceiveBuffer);
1120 Status = TpmMpDriver->Transmit (
1121 TpmMpDriver,
1122 TpmForceClearCommand,
1123 sizeof (TpmForceClearCommand),
1124 ReceiveBuffer,
1125 &ReceiveBufferSize
1126 );
1127 gRT->ResetSystem (
1128 EfiResetWarm,
1129 EFI_SUCCESS,
1130 0,
1131 NULL
1132 );
1133 }
1134 if (Data == 0x06)
1135 {
1136 //
1137 // TPM_PhysicalEnable
1138 //
1139 ReceiveBufferSize = sizeof(ReceiveBuffer);
1140 Status = TpmMpDriver->Transmit (
1141 TpmMpDriver,
1142 TpmPhysicalEnableCommand,
1143 sizeof (TpmPhysicalEnableCommand),
1144 ReceiveBuffer,
1145 &ReceiveBufferSize
1146 );
1147 //
1148 // TPM_PhysicalSetDeactivated=FALSE
1149 //
1150 ReceiveBufferSize = sizeof(ReceiveBuffer);
1151 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1152 Status = TpmMpDriver->Transmit (
1153 TpmMpDriver,
1154 TpmPhysicalSetDeactivatedCommand,
1155 sizeof (TpmPhysicalSetDeactivatedCommand),
1156 ReceiveBuffer,
1157 &ReceiveBufferSize
1158 );
1159 gRT->ResetSystem (
1160 EfiResetWarm,
1161 EFI_SUCCESS,
1162 0,
1163 NULL
1164 );
1165 }
1166 if (Data == 0x07)
1167 {
1168 //
1169 // TPM_PhysicalSetDeactivated=TRUE
1170 //
1171 ReceiveBufferSize = sizeof(ReceiveBuffer);
1172 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1173 Status = TpmMpDriver->Transmit (
1174 TpmMpDriver,
1175 TpmPhysicalSetDeactivatedCommand,
1176 sizeof (TpmPhysicalSetDeactivatedCommand),
1177 ReceiveBuffer,
1178 &ReceiveBufferSize
1179 );
1180 //
1181 // TPM_PhysicalDisable
1182 //
1183 ReceiveBufferSize = sizeof(ReceiveBuffer);
1184 Status = TpmMpDriver->Transmit (
1185 TpmMpDriver,
1186 TpmPhysicalDisableCommand,
1187 sizeof (TpmPhysicalDisableCommand),
1188 ReceiveBuffer,
1189 &ReceiveBufferSize
1190 );
1191 gRT->ResetSystem (
1192 EfiResetWarm,
1193 EFI_SUCCESS,
1194 0,
1195 NULL
1196 );
1197 }
1198 if (Data == 0x08)
1199 {
1200 //
1201 // TPM_SetOwnerInstall=TRUE
1202 //
1203 ReceiveBufferSize = sizeof(ReceiveBuffer);
1204 TpmSetOwnerInstallCommand [10] = 0x01;
1205 Status = TpmMpDriver->Transmit (
1206 TpmMpDriver,
1207 TpmSetOwnerInstallCommand,
1208 sizeof (TpmSetOwnerInstallCommand),
1209 ReceiveBuffer,
1210 &ReceiveBufferSize
1211 );
1212 }
1213 if (Data == 0x09)
1214 {
1215 //
1216 // TPM_SetOwnerInstall=FALSE
1217 //
1218 ReceiveBufferSize = sizeof(ReceiveBuffer);
1219 TpmSetOwnerInstallCommand [10] = 0x00;
1220 Status = TpmMpDriver->Transmit (
1221 TpmMpDriver,
1222 TpmSetOwnerInstallCommand,
1223 sizeof (TpmSetOwnerInstallCommand),
1224 ReceiveBuffer,
1225 &ReceiveBufferSize
1226 );
1227 }
1228 if (Data == 0x0A)
1229 {
1230 //
1231 // TPM_PhysicalEnable
1232 //
1233 ReceiveBufferSize = sizeof(ReceiveBuffer);
1234 Status = TpmMpDriver->Transmit (
1235 TpmMpDriver,
1236 TpmPhysicalEnableCommand,
1237 sizeof (TpmPhysicalEnableCommand),
1238 ReceiveBuffer,
1239 &ReceiveBufferSize
1240 );
1241 //
1242 // TPM_PhysicalSetDeactivated=FALSE
1243 //
1244 ReceiveBufferSize = sizeof(ReceiveBuffer);
1245 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1246 Status = TpmMpDriver->Transmit (
1247 TpmMpDriver,
1248 TpmPhysicalSetDeactivatedCommand,
1249 sizeof (TpmPhysicalSetDeactivatedCommand),
1250 ReceiveBuffer,
1251 &ReceiveBufferSize
1252 );
1253 //
1254 // Do TPM_SetOwnerInstall=TRUE on next reboot
1255 //
1256
1257 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
1258
1259 gRT->ResetSystem (
1260 EfiResetWarm,
1261 EFI_SUCCESS,
1262 0,
1263 NULL
1264 );
1265 }
1266 if (Data == 0x0B)
1267 {
1268 //
1269 // TPM_SetOwnerInstall=FALSE
1270 //
1271 ReceiveBufferSize = sizeof(ReceiveBuffer);
1272 TpmSetOwnerInstallCommand [10] = 0x00;
1273 Status = TpmMpDriver->Transmit (
1274 TpmMpDriver,
1275 TpmSetOwnerInstallCommand,
1276 sizeof (TpmSetOwnerInstallCommand),
1277 ReceiveBuffer,
1278 &ReceiveBufferSize
1279 );
1280 //
1281 // TPM_PhysicalSetDeactivated=TRUE
1282 //
1283 ReceiveBufferSize = sizeof(ReceiveBuffer);
1284 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1285 Status = TpmMpDriver->Transmit (
1286 TpmMpDriver,
1287 TpmPhysicalSetDeactivatedCommand,
1288 sizeof (TpmPhysicalSetDeactivatedCommand),
1289 ReceiveBuffer,
1290 &ReceiveBufferSize
1291 );
1292 //
1293 // TPM_PhysicalDisable
1294 //
1295 ReceiveBufferSize = sizeof(ReceiveBuffer);
1296 Status = TpmMpDriver->Transmit (
1297 TpmMpDriver,
1298 TpmPhysicalDisableCommand,
1299 sizeof (TpmPhysicalDisableCommand),
1300 ReceiveBuffer,
1301 &ReceiveBufferSize
1302 );
1303 gRT->ResetSystem (
1304 EfiResetWarm,
1305 EFI_SUCCESS,
1306 0,
1307 NULL
1308 );
1309 }
1310 if (Data == 0x0E)
1311 {
1312 //
1313 // TPM_ForceClear
1314 //
1315 ReceiveBufferSize = sizeof(ReceiveBuffer);
1316 Status = TpmMpDriver->Transmit (
1317 TpmMpDriver,
1318 TpmForceClearCommand,
1319 sizeof (TpmForceClearCommand),
1320 ReceiveBuffer,
1321 &ReceiveBufferSize
1322 );
1323 //
1324 // TPM_PhysicalEnable
1325 //
1326 ReceiveBufferSize = sizeof(ReceiveBuffer);
1327 Status = TpmMpDriver->Transmit (
1328 TpmMpDriver,
1329 TpmPhysicalEnableCommand,
1330 sizeof (TpmPhysicalEnableCommand),
1331 ReceiveBuffer,
1332 &ReceiveBufferSize
1333 );
1334 //
1335 // TPM_PhysicalSetDeactivated=FALSE
1336 //
1337 ReceiveBufferSize = sizeof(ReceiveBuffer);
1338 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1339 Status = TpmMpDriver->Transmit (
1340 TpmMpDriver,
1341 TpmPhysicalSetDeactivatedCommand,
1342 sizeof (TpmPhysicalSetDeactivatedCommand),
1343 ReceiveBuffer,
1344 &ReceiveBufferSize
1345 );
1346 gRT->ResetSystem (
1347 EfiResetWarm,
1348 EFI_SUCCESS,
1349 0,
1350 NULL
1351 );
1352 }
1353 if (Data == 0xF0)
1354 {
1355 //
1356 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1357 //
1358 ReceiveBufferSize = sizeof(ReceiveBuffer);
1359 TpmSetOwnerInstallCommand [10] = 0x01;
1360 Status = TpmMpDriver->Transmit (
1361 TpmMpDriver,
1362 TpmSetOwnerInstallCommand,
1363 sizeof (TpmSetOwnerInstallCommand),
1364 ReceiveBuffer,
1365 &ReceiveBufferSize
1366 );
1367 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
1368 }
1369 //
1370 // Deassert Physical Presence
1371 //
1372 TpmPhysicalPresenceCommand [11] = 0x10;
1373 ReceiveBufferSize = sizeof(ReceiveBuffer);
1374 Status = TpmMpDriver->Transmit (
1375 TpmMpDriver,
1376 TpmPhysicalPresenceCommand,
1377 sizeof (TpmPhysicalPresenceCommand),
1378 ReceiveBuffer,
1379 &ReceiveBufferSize
1380 );
1381 }
1382 }
1383
1384 return;
1385 }
1386
1387 /**
1388
1389 Initializes manufacturing and config mode setting.
1390
1391 **/
1392 VOID
1393 InitMfgAndConfigModeStateVar()
1394 {
1395 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1396 VOID *HobList;
1397 UINT16 State;
1398
1399 //
1400 // Variable initialization
1401 //
1402 State = FALSE;
1403
1404 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1405 if (HobList != NULL) {
1406 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1407
1408 //
1409 // Check if in Manufacturing mode
1410 //
1411 if ( !CompareMem (
1412 &BootModeBuffer->SetupName,
1413 MANUFACTURE_SETUP_NAME,
1414 StrSize (MANUFACTURE_SETUP_NAME)
1415 ) ) {
1416 mMfgMode = TRUE;
1417 }
1418
1419 //
1420 // Check if in safe mode
1421 //
1422 if ( !CompareMem (
1423 &BootModeBuffer->SetupName,
1424 SAFE_SETUP_NAME,
1425 StrSize (SAFE_SETUP_NAME)
1426 ) ) {
1427 State = TRUE;
1428 }
1429 }
1430
1431 }
1432
1433 /**
1434
1435 Initializes manufacturing and config mode setting.
1436
1437 **/
1438 VOID
1439 InitPlatformBootMode()
1440 {
1441 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1442 VOID *HobList;
1443
1444 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1445 if (HobList != NULL) {
1446 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1447 mPlatformBootMode = BootModeBuffer->PlatformBootMode;
1448 }
1449 }
1450
1451 /**
1452
1453 Initializes ITK.
1454
1455 **/
1456 VOID
1457 InitItk(
1458 )
1459 {
1460 EFI_STATUS Status;
1461 UINT16 ItkModBiosState;
1462 UINT8 Value;
1463 UINTN DataSize;
1464 UINT32 Attributes;
1465
1466 //
1467 // Setup local variable according to ITK variable
1468 //
1469 //
1470 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1471 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1472 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1473 //
1474 DataSize = sizeof (Value);
1475 Status = gRT->GetVariable (
1476 ITK_BIOS_MOD_VAR_NAME,
1477 &gItkDataVarGuid,
1478 &Attributes,
1479 &DataSize,
1480 &Value
1481 );
1482 if (Status == EFI_NOT_FOUND) {
1483 //
1484 // Variable not found, hasn't been initialized, intialize to 0
1485 //
1486 Value=0x00;
1487 //
1488 // Write variable to flash.
1489 //
1490 gRT->SetVariable (
1491 ITK_BIOS_MOD_VAR_NAME,
1492 &gItkDataVarGuid,
1493 EFI_VARIABLE_RUNTIME_ACCESS |
1494 EFI_VARIABLE_NON_VOLATILE |
1495 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1496 sizeof (Value),
1497 &Value
1498 );
1499
1500 }
1501 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
1502 if (Value == 0x00) {
1503 ItkModBiosState = 0x00;
1504 } else {
1505 ItkModBiosState = 0x01;
1506 }
1507 gRT->SetVariable (
1508 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
1509 &gEfiNormalSetupGuid,
1510 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1511 2,
1512 (void *)&ItkModBiosState
1513 );
1514 }
1515 }
1516
1517 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1518
1519 /**
1520
1521 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1522
1523 **/
1524 STATIC
1525 VOID
1526 InitFirmwareId(
1527 )
1528 {
1529 EFI_STATUS Status;
1530 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
1531
1532 //
1533 // First try writing the variable without a password in case we are
1534 // upgrading from a BIOS without password protection on the FirmwareId
1535 //
1536 Status = gRT->SetVariable(
1537 (CHAR16 *)&gFirmwareIdName,
1538 &gFirmwareIdGuid,
1539 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1540 EFI_VARIABLE_RUNTIME_ACCESS,
1541 sizeof( FIRMWARE_ID ) - 1,
1542 FIRMWARE_ID
1543 );
1544
1545 if (Status == EFI_INVALID_PARAMETER) {
1546
1547 //
1548 // Since setting the firmware id without the password failed,
1549 // a password must be required.
1550 //
1551 Status = gRT->SetVariable(
1552 (CHAR16 *)&FirmwareIdNameWithPassword,
1553 &gFirmwareIdGuid,
1554 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1555 EFI_VARIABLE_RUNTIME_ACCESS,
1556 sizeof( FIRMWARE_ID ) - 1,
1557 FIRMWARE_ID
1558 );
1559 }
1560 }
1561 #endif
1562
1563 VOID
1564 UpdateDVMTSetup(
1565 )
1566 {
1567 //
1568 // Workaround to support IIA bug.
1569 // IIA request to change option value to 4, 5 and 7 relatively
1570 // instead of 1, 2, and 3 which follow Lakeport Specs.
1571 // Check option value, temporary hardcode GraphicsDriverMemorySize
1572 // Option value to fulfill IIA requirment. So that user no need to
1573 // load default and update setupvariable after update BIOS.
1574 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1575 // *This is for broadwater and above product only.
1576 //
1577
1578 SYSTEM_CONFIGURATION SystemConfiguration;
1579 UINTN VarSize;
1580 EFI_STATUS Status;
1581
1582 VarSize = sizeof(SYSTEM_CONFIGURATION);
1583 Status = gRT->GetVariable(
1584 NORMAL_SETUP_NAME,
1585 &gEfiNormalSetupGuid,
1586 NULL,
1587 &VarSize,
1588 &SystemConfiguration
1589 );
1590
1591 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
1592 switch (SystemConfiguration.GraphicsDriverMemorySize){
1593 case 1:
1594 SystemConfiguration.GraphicsDriverMemorySize = 4;
1595 break;
1596 case 2:
1597 SystemConfiguration.GraphicsDriverMemorySize = 5;
1598 break;
1599 case 3:
1600 SystemConfiguration.GraphicsDriverMemorySize = 7;
1601 break;
1602 default:
1603 break;
1604 }
1605
1606 Status = gRT->SetVariable (
1607 NORMAL_SETUP_NAME,
1608 &gEfiNormalSetupGuid,
1609 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
1610 sizeof(SYSTEM_CONFIGURATION),
1611 &SystemConfiguration
1612 );
1613 }
1614 }
1615
1616 VOID
1617 InitPlatformUsbPolicy (
1618 VOID
1619 )
1620
1621 {
1622 EFI_HANDLE Handle;
1623 EFI_STATUS Status;
1624
1625 Handle = NULL;
1626
1627 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
1628 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
1629 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
1630 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
1631 } else {
1632 mUsbPolicyData.UsbEmulationSize = 0;
1633 }
1634 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
1635 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
1636
1637 //
1638 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1639 //
1640 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
1641
1642 //
1643 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1644 //
1645 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
1646
1647 //
1648 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1649 //
1650 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
1651
1652 //
1653 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1654 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1655 mUsbPolicyData.LpcAcpiBase = 0x40;
1656 mUsbPolicyData.AcpiTimerReg = 0x08;
1657
1658 //
1659 // Set for reduce usb post time
1660 //
1661 mUsbPolicyData.UsbTimeTue = 0x00;
1662 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
1663 mUsbPolicyData.EnumWaitPortStableStall = 100;
1664
1665
1666 Status = gBS->InstallProtocolInterface (
1667 &Handle,
1668 &gUsbPolicyGuid,
1669 EFI_NATIVE_INTERFACE,
1670 &mUsbPolicyData
1671 );
1672 ASSERT_EFI_ERROR(Status);
1673
1674 }
1675
1676 UINT8
1677 ReadCmosBank1Byte (
1678 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1679 IN UINT8 Index
1680 )
1681 {
1682 UINT8 Data;
1683
1684 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
1685 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
1686 return Data;
1687 }
1688
1689 VOID
1690 WriteCmosBank1Byte (
1691 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1692 IN UINT8 Index,
1693 IN UINT8 Data
1694 )
1695 {
1696 CpuIo->Io.Write (
1697 CpuIo,
1698 EfiCpuIoWidthUint8,
1699 0x72,
1700 1,
1701 &Index
1702 );
1703 CpuIo->Io.Write (
1704 CpuIo,
1705 EfiCpuIoWidthUint8,
1706 0x73,
1707 1,
1708 &Data
1709 );
1710 }
1711
EFI Development Kit II mirror for PVE