Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c

   1 /** @file
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 Module Name:
  15
  16   MemoryCallback.c
  17
  18 Abstract:
  19
  20   EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.
  21
  22 --*/
  23
  24 #include "PlatformEarlyInit.h"
  25
  26
  27 VOID
  28 UpdateDefaultSetupValue (
  29   IN  EFI_PLATFORM_INFO_HOB       *PlatformInfo
  30   )
  31 {
  32 return;
  33 }
  34
  35 /**
  36   PEI termination callback.
  37
  38   @param PeiServices         General purpose services available to every PEIM.
  39   @param NotifyDescriptor    Not uesed.
  40   @param Ppi                 Not uesed.
  41
  42   @retval EFI_SUCCESS        If the interface could be successfully
  43                              installed.
  44
  45 **/
  46 EFI_STATUS
  47 EFIAPI
  48 EndOfPeiPpiNotifyCallback (
  49   IN CONST EFI_PEI_SERVICES           **PeiServices,
  50   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
  51   IN VOID                       *Ppi
  52   )
  53 {
  54   EFI_STATUS                  Status;
  55   UINT64                      MemoryTop;
  56   UINT64                      LowUncableBase;
  57   EFI_PLATFORM_INFO_HOB       *PlatformInfo;
  58   UINT32                      HecBaseHigh;
  59   EFI_BOOT_MODE               BootMode;
  60   EFI_PEI_HOB_POINTERS        Hob;
  61
  62   Status = (*PeiServices)->GetBootMode(
  63                              PeiServices,
  64                              &BootMode
  65                              );
  66
  67   ASSERT_EFI_ERROR (Status);
  68
  69   //
  70   // Set the some PCI and chipset range as UC
  71   // And align to 1M at leaset
  72   //
  73   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  74   ASSERT (Hob.Raw != NULL);
  75   PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
  76
  77   UpdateDefaultSetupValue (PlatformInfo);
  78
  79   DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));
  80   DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));
  81   DEBUG (
  82     (EFI_D_ERROR,
  83     "PCIE   BASE: %lX     Size : %X\n",
  84     PlatformInfo->PciData.PciExpressBase,
  85     PlatformInfo->PciData.PciExpressSize)
  86     );
  87   DEBUG (
  88     (EFI_D_ERROR,
  89     "PCI32  BASE: %X     Limit: %X\n",
  90     PlatformInfo->PciData.PciResourceMem32Base,
  91     PlatformInfo->PciData.PciResourceMem32Limit)
  92     );
  93   DEBUG (
  94     (EFI_D_ERROR,
  95     "PCI64  BASE: %lX     Limit: %lX\n",
  96     PlatformInfo->PciData.PciResourceMem64Base,
  97     PlatformInfo->PciData.PciResourceMem64Limit)
  98     );
  99   DEBUG ((EFI_D_ERROR, "UC    START: %lX     End  : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));
 100
 101   LowUncableBase = PlatformInfo->MemData.MemMaxTolm;
 102   LowUncableBase &= (0x0FFF00000);
 103   MemoryTop = (0x100000000);
 104
 105   if (BootMode != BOOT_ON_S3_RESUME) {
 106     //
 107     // In BIOS, HECBASE will be always below 4GB
 108     //
 109     HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);
 110     ASSERT (HecBaseHigh < 16);
 111   }
 112
 113   return Status;
 114 }
 115
 116 /**
 117   Install Firmware Volume Hob's once there is main memory
 118
 119   @param PeiServices       General purpose services available to every PEIM.
 120   @param NotifyDescriptor  Notify that this module published.
 121   @param Ppi               PPI that was installed.
 122
 123   @retval EFI_SUCCESS     The function completed successfully.
 124
 125 **/
 126 EFI_STATUS
 127 EFIAPI
 128 MemoryDiscoveredPpiNotifyCallback (
 129   IN CONST EFI_PEI_SERVICES           **PeiServices,
 130   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 131   IN VOID                       *Ppi
 132   )
 133 {
 134   EFI_STATUS                  Status;
 135   EFI_BOOT_MODE               BootMode;
 136   EFI_CPUID_REGISTER          FeatureInfo;
 137   UINT8                       CpuAddressWidth;
 138   UINT16                      Pm1Cnt;
 139   EFI_PEI_HOB_POINTERS        Hob;
 140   EFI_PLATFORM_INFO_HOB       *PlatformInfo;
 141   UINT32                      RootComplexBar;
 142   UINT32                      PmcBase;
 143   UINT32                      IoBase;
 144   UINT32                      IlbBase;
 145   UINT32                      SpiBase;
 146   UINT32                      MphyBase;
 147
 148   //
 149   // Get Platform Info HOB
 150   //
 151   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
 152   ASSERT (Hob.Raw != NULL);
 153   PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
 154
 155   Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
 156
 157   //
 158   // Check if user wants to turn off in PEI phase
 159   //
 160   if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
 161     CheckPowerOffNow();
 162   } else {
 163     Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
 164     Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
 165     IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
 166   }
 167
 168   #ifndef MINNOW2_FSP_BUILD
 169   //
 170   // Set PEI cache mode here
 171   //
 172   SetPeiCacheMode (PeiServices);
 173   #endif
 174
 175   //
 176   //  Pulish memory tyoe info
 177   //
 178   PublishMemoryTypeInfo ();
 179
 180   //
 181   // Work done if on a S3 resume
 182   //
 183   if (BootMode == BOOT_ON_S3_RESUME) {
 184     //
 185     //Program the side band packet register to send a sideband message to Punit
 186     //To indicate that DRAM has been initialized and PUNIT FW base address in memory.
 187     //
 188     return EFI_SUCCESS;
 189   }
 190
 191   RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;
 192   BuildResourceDescriptorHob (
 193     EFI_RESOURCE_MEMORY_MAPPED_IO,
 194     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 195     RootComplexBar,
 196     0x1000
 197     );
 198   DEBUG ((EFI_D_INFO, "RootComplexBar     : 0x%x\n", RootComplexBar));
 199
 200   PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;
 201   BuildResourceDescriptorHob (
 202     EFI_RESOURCE_MEMORY_MAPPED_IO,
 203     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 204     PmcBase,
 205     0x1000
 206     );
 207   DEBUG ((EFI_D_INFO, "PmcBase            : 0x%x\n", PmcBase));
 208
 209   IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
 210   BuildResourceDescriptorHob (
 211     EFI_RESOURCE_MEMORY_MAPPED_IO,
 212     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 213     IoBase,
 214     0x4000
 215     );
 216   DEBUG ((EFI_D_INFO, "IoBase             : 0x%x\n", IoBase));
 217
 218   IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;
 219   BuildResourceDescriptorHob (
 220     EFI_RESOURCE_MEMORY_MAPPED_IO,
 221     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 222     IlbBase,
 223     0x1000
 224     );
 225   DEBUG ((EFI_D_INFO, "IlbBase            : 0x%x\n", IlbBase));
 226
 227   SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;
 228   BuildResourceDescriptorHob (
 229     EFI_RESOURCE_MEMORY_MAPPED_IO,
 230     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 231     SpiBase,
 232     0x1000
 233     );
 234   DEBUG ((EFI_D_INFO, "SpiBase            : 0x%x\n", SpiBase));
 235
 236   MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;
 237   BuildResourceDescriptorHob (
 238     EFI_RESOURCE_MEMORY_MAPPED_IO,
 239     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 240     MphyBase,
 241     0x100000
 242     );
 243   DEBUG ((EFI_D_INFO, "MphyBase           : 0x%x\n", MphyBase));
 244
 245   //
 246   // Local APIC
 247   //
 248   BuildResourceDescriptorHob (
 249     EFI_RESOURCE_MEMORY_MAPPED_IO,
 250     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 251     LOCAL_APIC_ADDRESS,
 252     0x1000
 253   );
 254   DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));
 255
 256   //
 257   // IO APIC
 258   //
 259   BuildResourceDescriptorHob (
 260     EFI_RESOURCE_MEMORY_MAPPED_IO,
 261     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 262     IO_APIC_ADDRESS,
 263     0x1000
 264   );
 265   DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS    : 0x%x\n", IO_APIC_ADDRESS));
 266
 267   //
 268   // Adding the PCIE Express area to the E820 memory table as type 2 memory.
 269   //
 270   BuildResourceDescriptorHob (
 271     EFI_RESOURCE_MEMORY_MAPPED_IO,
 272     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 273     PlatformInfo->PciData.PciExpressBase,
 274     PlatformInfo->PciData.PciExpressSize
 275     );
 276   DEBUG ((EFI_D_INFO, "PciExpressBase     : 0x%x\n", PlatformInfo->PciData.PciExpressBase));
 277
 278   //
 279   // Adding the Flashpart to the E820 memory table as type 2 memory.
 280   //
 281   BuildResourceDescriptorHob (
 282     EFI_RESOURCE_FIRMWARE_DEVICE,
 283     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 284     FixedPcdGet32 (PcdFlashAreaBaseAddress),
 285     FixedPcdGet32 (PcdFlashAreaSize)
 286     );
 287   DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));
 288
 289   //
 290   // Create a CPU hand-off information
 291   //
 292   CpuAddressWidth = 32;
 293   AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
 294   if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
 295     AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
 296     CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
 297   }
 298
 299   BuildCpuHob(CpuAddressWidth, 16);
 300   ASSERT_EFI_ERROR (Status);
 301
 302   return Status;
 303
 304 }
 305
 306
 307 EFI_STATUS
 308 ValidateFvHeader (
 309   IN EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader
 310   )
 311 {
 312   UINT16  *Ptr;
 313   UINT16  HeaderLength;
 314   UINT16  Checksum;
 315
 316   //
 317   // Verify the header revision, header signature, length
 318   // Length of FvBlock cannot be 2**64-1
 319   // HeaderLength cannot be an odd number
 320   //
 321   if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
 322       (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
 323       (FwVolHeader->FvLength == ((UINT64) -1)) ||
 324       ((FwVolHeader->HeaderLength & 0x01) != 0)
 325       ) {
 326     return EFI_NOT_FOUND;
 327   }
 328
 329   //
 330   // Verify the header checksum
 331   //
 332   HeaderLength  = (UINT16) (FwVolHeader->HeaderLength / 2);
 333   Ptr           = (UINT16 *) FwVolHeader;
 334   Checksum      = 0;
 335   while (HeaderLength > 0) {
 336     Checksum = *Ptr++;
 337     HeaderLength--;
 338   }
 339
 340   if (Checksum != 0) {
 341     return EFI_NOT_FOUND;
 342   }
 343
 344   return EFI_SUCCESS;
 345 }