Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c

   1
   2 /*++
   3
   4 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9
  10
  11 Module Name:
  12
  13   VlvPlatformInit.c
  14
  15 Abstract:
  16
  17   This is the driver that initializes the Intel ValleyView.
  18
  19 --*/
  20
  21 #include "VlvPlatformInit.h"
  22 #include <Protocol/VlvPlatformPolicy.h>
  23
  24 extern DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;
  25 UINT64            GTTMMADR;
  26
  27 DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;
  28
  29 /**
  30   "Poll Status" for GT Readiness
  31
  32  @param  Base             Base address of MMIO
  33  @param  Offset           MMIO Offset
  34  @param  Mask             Mask
  35  @param  Result           Value to wait for
  36
  37  @retval None
  38
  39 **/
  40 VOID
  41 PollGtReady_hang (
  42   UINT64 Base,
  43   UINT32 Offset,
  44   UINT32 Mask,
  45   UINT32 Result
  46   )
  47 {
  48   UINT32  GtStatus;
  49
  50   //
  51   // Register read
  52   //
  53   GtStatus = MmioRead32 ((UINTN)Base+ Offset);
  54
  55   while (((GtStatus & Mask) != Result)) {
  56
  57     GtStatus = MmioRead32 ((UINTN)Base + Offset);
  58   }
  59
  60 }
  61
  62 /**
  63   Do Post GT PM Init Steps after VBIOS Initialization.
  64
  65   @param Event             A pointer to the Event that triggered the callback.
  66   @param Context           A pointer to private data registered with the callback function.
  67
  68   @retval EFI_SUCCESS        GC_TODO
  69
  70
  71 **/
  72 EFI_STATUS
  73 EFIAPI
  74 PostPmInitCallBack (
  75   IN EFI_EVENT Event,
  76   IN VOID      *Context
  77   )
  78 {
  79   UINT64      OriginalGTTMMADR;
  80   UINT32      LoGTBaseAddress;
  81   UINT32      HiGTBaseAddress;
  82
  83   //
  84   // Enable Bus Master, I/O and Memory access on 0:2:0
  85   //
  86   PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
  87
  88   //
  89   // only 32bit read/write is legal for device 0:2:0
  90   //
  91   OriginalGTTMMADR  = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));
  92   OriginalGTTMMADR  = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
  93
  94   //
  95   // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
  96   // Program temporarily 32bits GTTMMADR for POST and S3 resume
  97   //
  98   LoGTBaseAddress                   = (UINT32) (GTTMMADR & 0xFFFFFFFF);
  99   HiGTBaseAddress                   = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);
 100   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
 101   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
 102
 103
 104
 105   //
 106   // Restore original GTTMMADR
 107   //
 108   LoGTBaseAddress                   = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
 109   HiGTBaseAddress                   = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);
 110
 111   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
 112   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
 113
 114
 115   //
 116   // Lock the following registers, GGC, BDSM, BGSM
 117   //
 118   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
 119   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
 120   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
 121
 122   gBS->CloseEvent (Event);
 123
 124   //
 125   // Return final status
 126   //
 127   return EFI_SUCCESS;
 128 }
 129
 130 /**
 131
 132   Routine Description:
 133
 134   Initialize GT Post Routines.
 135
 136   @param ImageHandle              Handle for the image of this driver
 137   @param DxePlatformSaPolicy      SA DxePlatformPolicy protocol
 138
 139   @retval EFI_SUCCESS             GT POST initialization complete
 140
 141 **/
 142 EFI_STATUS
 143 IgdPmHook (
 144   IN EFI_HANDLE                      ImageHandle,
 145   IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicyParam
 146   )
 147 {
 148
 149   EFI_EVENT             mConOutEvent;
 150   VOID                  *gConOutNotifyReg;
 151
 152   EFI_STATUS            Status;
 153
 154   EFI_PHYSICAL_ADDRESS  MemBaseAddress;
 155   UINT32                LoGTBaseAddress;
 156   UINT32                HiGTBaseAddress;
 157
 158   GTTMMADR    = 0;
 159   Status      = EFI_SUCCESS;
 160
 161   //
 162   // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
 163   //
 164   if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID))  != 0xFFFF) {
 165
 166     ASSERT (gDS!=NULL);
 167
 168     //
 169     // Enable Bus Master, I/O and Memory access on 0:2:0
 170     //
 171     PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));
 172
 173     //
 174     // Means Allocate 4MB for GTTMADDR
 175     //
 176     MemBaseAddress = 0x0ffffffff;
 177
 178     Status = gDS->AllocateMemorySpace (
 179                     EfiGcdAllocateMaxAddressSearchBottomUp,
 180                     EfiGcdMemoryTypeMemoryMappedIo,
 181                     GTT_MEM_ALIGN,
 182                     GTTMMADR_SIZE_4MB,
 183                     &MemBaseAddress,
 184                     ImageHandle,
 185                     NULL
 186                     );
 187     ASSERT_EFI_ERROR (Status);
 188
 189     //
 190     // Program GT PM Settings if GTTMMADR allocation is Successful
 191     //
 192     GTTMMADR                          = (UINTN) MemBaseAddress;
 193
 194     LoGTBaseAddress                   = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
 195     HiGTBaseAddress                   = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);
 196
 197     PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);
 198     PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);
 199
 200
 201     S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));
 202
 203
 204     S3MmioRead32(IGD_R_GTTMMADR + 4);
 205
 206
 207     S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));
 208
 209     //
 210     // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack
 211     //
 212     Status = gBS->CreateEvent (
 213                     EVT_NOTIFY_SIGNAL,
 214                     TPL_CALLBACK,
 215                     (EFI_EVENT_NOTIFY)PostPmInitCallBack,
 216                     NULL,
 217                     &mConOutEvent
 218                     );
 219
 220     ASSERT_EFI_ERROR (Status);
 221     if (EFI_ERROR (Status)) {
 222       return Status;
 223     }
 224
 225
 226     Status = gBS->RegisterProtocolNotify (
 227                     &gEfiGraphicsOutputProtocolGuid,
 228                     mConOutEvent,
 229                     &gConOutNotifyReg
 230                     );
 231
 232
 233
 234     MmioWrite64 (IGD_R_GTTMMADR, 0);
 235
 236     //
 237     // Free allocated resources
 238     //
 239     gDS->FreeMemorySpace (
 240            MemBaseAddress,
 241            GTTMMADR_SIZE_4MB
 242            );
 243
 244   }
 245
 246   return EFI_SUCCESS;
 247 }
 248
 249 /**
 250
 251   This is the standard EFI driver point that detects
 252   whether there is an ICH southbridge in the system
 253   and if so, initializes the chip.
 254
 255   @param  ImageHandle             Handle for the image of this driver
 256   @param  SystemTable             Pointer to the EFI System Table
 257
 258   @retval EFI_SUCCESS             The function completed successfully
 259
 260 **/
 261 EFI_STATUS
 262 EFIAPI
 263 VlvPlatformInitEntryPoint (
 264   IN EFI_HANDLE       ImageHandle,
 265   IN EFI_SYSTEM_TABLE *SystemTable
 266   )
 267 {
 268   EFI_STATUS                        Status;
 269
 270   Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);
 271   ASSERT_EFI_ERROR (Status);
 272
 273   //
 274   // GtPostInit Initialization
 275   //
 276   DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));
 277   IgdPmHook (ImageHandle, DxePlatformSaPolicy);
 278
 279   //
 280   // IgdOpRegion Install Initialization
 281   //
 282   DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));
 283   IgdOpRegionInit ();
 284
 285   return EFI_SUCCESS;
 286 }
 287