# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.\r
#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#**/\r
\r
Include # Root include for the package\r
\r
[LibraryClasses.common]\r
- ArmLib|Include/Library/ArmLib.h\r
- ArmMmuLib|Include/Library/ArmMmuLib.h\r
- SemihostLib|Include/Library/Semihosting.h\r
- DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
+ ## @libraryclass Convert Arm instructions to a human readable format.\r
+ #\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
+\r
+ ## @libraryclass Provides an interface to Arm generic counters.\r
+ #\r
+ ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h\r
+\r
+ ## @libraryclass Provides an interface to initialize a\r
+ # Generic Interrupt Controller (GIC).\r
+ #\r
ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
+\r
+ ## @libraryclass Provides a Generic Interrupt Controller (GIC)\r
+ # configuration interface.\r
+ #\r
+ ArmGicLib|Include/Library/ArmGicLib.h\r
+\r
+ ## @libraryclass Provides a HyperVisor Call (HVC) interface.\r
+ #\r
+ ArmHvcLib|Include/Library/ArmHvcLib.h\r
+\r
+ ## @libraryclass Provides an interface to Arm registers.\r
+ #\r
+ ArmLib|Include/Library/ArmLib.h\r
+\r
+ ## @libraryclass Provides a Mmu interface.\r
+ #\r
+ ArmMmuLib|Include/Library/ArmMmuLib.h\r
+\r
+ ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface\r
+ # for the System Control and Management Interface (SCMI).\r
+ #\r
+ ArmMtlLib|Include/Library/ArmMtlLib.h\r
+\r
+ ## @libraryclass Provides a System Monitor Call (SMC) interface.\r
+ #\r
+ ArmSmcLib|Include/Library/ArmSmcLib.h\r
+\r
+ ## @libraryclass Provides a SuperVisor Call (SVC) interface.\r
+ #\r
ArmSvcLib|Include/Library/ArmSvcLib.h\r
\r
+ ## @libraryclass Provides a default exception handler.\r
+ #\r
+ DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
+\r
+ ## @libraryclass Provides an interface to query miscellaneous OEM\r
+ # information.\r
+ #\r
+ OemMiscLib|Include/Library/OemMiscLib.h\r
+\r
+ ## @libraryclass Provides an OpTee interface.\r
+ #\r
+ OpteeLib|Include/Library/OpteeLib.h\r
+\r
+ ## @libraryclass Provides a semihosting interface.\r
+ #\r
+ SemihostLib|Include/Library/SemihostLib.h\r
+\r
+ ## @libraryclass Provides an interface for a StandaloneMm Mmu.\r
+ #\r
+ StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r
+\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
# Include/Guid/ArmMpCoreInfo.h\r
gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
- gArmGicDxeFileGuid = { 0xde371f7c, 0xdec4, 0x4d21, { 0xad, 0xf1, 0x59, 0x3a, 0xbc, 0xc1, 0x58, 0x82 } }\r
+[Protocols.common]\r
+ ## Arm System Control and Management Interface(SCMI) Base protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
+ gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
+ gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
+ gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
+ gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
\r
[Ppis]\r
## Include/Ppi/ArmMpCoreInfo.h\r
# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
- # Define if the spin-table mechanism is used by the secondary cores when booting\r
- # Linux (instead of PSCI)\r
- gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
-\r
# Define if the GICv3 controller should use the GICv2 legacy\r
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
# hardware coherency (i.e., no virtualization or cache coherent DMA)\r
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
\r
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]\r
+ ## Used to select method for requesting services from S-EL1.<BR><BR>\r
+ # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r
+ # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r
+ # @Prompt Enable FF-A support.\r
+ gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r
+\r
[PcdsFixedAtBuild.common]\r
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
# The Primary Core is ClusterId[0] & CoreId[0]\r
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
+ #\r
+ # SMBIOS PCDs\r
+ #\r
+ gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r
+ gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r
+ gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r
+ gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r
+ gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r
+ gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r
+ gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r
+ gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r
+ gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r
+ gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r
+\r
#\r
# ARM L2x0 PCDs\r
#\r
# By default we do not do a transition to non-secure mode\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
\r
- # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
-\r
- # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
- # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
- # (see the kernel doc: Documentation/arm/Booting)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 64bit aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
-\r
# Non Secure Access Control Register\r
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
# Other modes include using SP0 or switching to Aarch32, but these are\r
# not currently supported.\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
- # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
- # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
- # (see the kernel doc: Documentation/arm64/booting.txt)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 2MB aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
#\r
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
+ gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
+ gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
+\r
+ gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r
+ gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r
+\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
#\r
- # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
- # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
- # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
#\r
# because (a) the target address space (ie. the cpu-physical space) is\r
# 64-bit, and (b) the translation values are meant as offsets for *modular*\r
# UINT64 TranslatedMmio64Address; // output parameter\r
#\r
# TranslatedIoAddress = UntranslatedIoAddress +\r
- # PcdPciIoTranslation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;\r
# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
- # PcdPciMmio32Translation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;\r
# TranslatedMmio64Address = UntranslatedMmio64Address +\r
- # PcdPciMmio64Translation;\r
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;\r
#\r
# The modular arithmetic performed in UINT64 ensures that the translation\r
# works correctly regardless of the relation between IoCpuBase and\r
#\r
gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
- gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
- gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
- gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
\r
#\r
# Inclusive range of allowed PCI buses.\r
#\r
gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r
+\r
+[PcdsDynamicEx]\r
+ #\r
+ # This dynamic PCD hold the GUID of a firmware FFS which contains\r
+ # the LinuxBoot payload.\r
+ #\r
+ gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C\r
projects / mirror_edk2.git / blobdiff