\r
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
-Portions copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r
+Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
--*/\r
\r
+#include <Library/ArmGicLib.h>\r
+\r
#include "ArmGicDxe.h"\r
-#include "GicV2/ArmGicV2Lib.h"\r
\r
#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EnableInterruptSource (\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
- if (Source > mGicNumInterrupts) {\r
+ if (Source >= mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2DisableInterruptSource (\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
- if (Source > mGicNumInterrupts) {\r
+ if (Source >= mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2GetInterruptSourceState (\r
IN BOOLEAN *InterruptState\r
)\r
{\r
- if (Source > mGicNumInterrupts) {\r
+ if (Source >= mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
+STATIC\r
EFI_STATUS\r
EFIAPI\r
GicV2EndOfInterrupt (\r
IN HARDWARE_INTERRUPT_SOURCE Source\r
)\r
{\r
- if (Source > mGicNumInterrupts) {\r
+ if (Source >= mGicNumInterrupts) {\r
ASSERT(FALSE);\r
return EFI_UNSUPPORTED;\r
}\r
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
@param InterruptType Defines the type of interrupt or exception that\r
- occurred on the processor.This parameter is processor architecture specific.\r
+ occurred on the processor.This parameter is\r
+ processor architecture specific.\r
@param SystemContext A pointer to the processor context when\r
the interrupt occurred on the processor.\r
\r
@return None\r
\r
**/\r
+STATIC\r
VOID\r
EFIAPI\r
GicV2IrqInterruptHandler (\r
\r
GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the\r
+ // number of interrupt (ie: Spurious interrupt).\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
- // The special interrupt do not need to be acknowledge\r
+ // The special interrupts do not need to be acknowledged\r
return;\r
}\r
\r
// Call the registered interrupt handler.\r
InterruptHandler (GicInterrupt, SystemContext);\r
} else {\r
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
+ DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
+ GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
}\r
-\r
- GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
}\r
\r
-//\r
// The protocol instance produced by this driver\r
-//\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {\r
RegisterInterruptSource,\r
GicV2EnableInterruptSource,\r
/**\r
Shutdown our hardware\r
\r
- DXE Core will disable interrupts and turn off the timer and disable interrupts\r
- after all the event handlers have run.\r
+ DXE Core will disable interrupts and turn off the timer and disable\r
+ interrupts after all the event handlers have run.\r
\r
@param[in] Event The Event that is being processed\r
@param[in] Context Event Context\r
**/\r
+STATIC\r
VOID\r
EFIAPI\r
GicV2ExitBootServicesEvent (\r
UINTN RegShift;\r
UINT32 CpuTarget;\r
\r
- // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+ // Make sure the Interrupt Controller Protocol is not already installed in\r
+ // the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
- mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);\r
- mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);\r
+ mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);\r
+ mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);\r
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
);\r
}\r
\r
- //\r
// Targets the interrupts to the Primary Cpu\r
- //\r
-\r
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
- //\r
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
- // first SGIs)\r
+\r
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by\r
+ // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn\r
+ // are banked to each connected CPU. These 8 registers hold the CPU targets\r
+ // fields for interrupts 0-31. More Info in the GIC Specification about\r
+ // "Interrupt Processor Targets Registers"\r
+\r
+ // Read the first Interrupt Processor Targets Register (that corresponds to\r
+ // the 4 first SGIs)\r
CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r
\r
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
- // is 0 when we run on a uniprocessor platform.\r
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.\r
+ // This value is 0 when we run on a uniprocessor platform.\r
if (CpuTarget != 0) {\r
// The 8 first Interrupt Processor Targets Registers are read-only\r
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+ MmioWrite32 (\r
+ mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),\r
+ CpuTarget\r
+ );\r
}\r
}\r
\r
ArmGicEnableDistributor (mGicDistributorBase);\r
\r
Status = InstallAndRegisterInterruptService (\r
- &gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);\r
+ &gHardwareInterruptV2Protocol,\r
+ GicV2IrqInterruptHandler,\r
+ GicV2ExitBootServicesEvent\r
+ );\r
\r
return Status;\r
}\r
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