\r
#include <Guid/IdleLoopEvent.h>\r
\r
-BOOLEAN mInterruptState = FALSE;\r
-\r
\r
/**\r
This function flushes the range of addresses from Start to Start+Length\r
\r
@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
the processor's data cache.\r
- @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
+ @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r
by FlushType.\r
@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
from the processor's data cache.\r
{\r
ArmEnableInterrupts ();\r
\r
- mInterruptState = TRUE;\r
return EFI_SUCCESS;\r
}\r
\r
{\r
ArmDisableInterrupts ();\r
\r
- mInterruptState = FALSE;\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- *State = mInterruptState;\r
+ *State = ArmGetInterruptState();\r
return EFI_SUCCESS;\r
}\r
\r
CpuGetTimerValue,\r
CpuSetMemoryAttributes,\r
0, // NumberOfTimers\r
- 4, // DmaBufferAlignment\r
+ 2048, // DmaBufferAlignment\r
};\r
\r
+STATIC\r
+VOID\r
+InitializeDma (\r
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
+ )\r
+{\r
+ CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
+}\r
+\r
EFI_STATUS\r
CpuDxeInitialize (\r
IN EFI_HANDLE ImageHandle,\r
\r
InitializeExceptions (&mCpu);\r
\r
+ InitializeDma (&mCpu);\r
+\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&mCpuHandle,\r
&gEfiCpuArchProtocolGuid, &mCpu,\r