ArmPkg/CpuDxe: set DmaBufferAlignment according to CWG

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / CpuDxe.c

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
index b1cac31d671b50e8dbb6c4b3cb037522d34de896..7d328d096b1e498567d3b9e59775a39f645d933a 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -39,7 +39,7 @@
 \r
   @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
                                 the processor's data cache.\r
-  @retval EFI_UNSUPPORTEDT      The processor does not support the cache flush type specified\r
+  @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified\r
                                 by FlushType.\r
   @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
                                 from the processor's data cache.\r
@@ -225,9 +225,18 @@ EFI_CPU_ARCH_PROTOCOL mCpu = {
   CpuGetTimerValue,\r
   CpuSetMemoryAttributes,\r
   0,          // NumberOfTimers\r
-  4,          // DmaBufferAlignment\r
+  2048,       // DmaBufferAlignment\r
 };\r
 \r
+STATIC\r
+VOID\r
+InitializeDma (\r
+  IN OUT  EFI_CPU_ARCH_PROTOCOL   *CpuArchProtocol\r
+  )\r
+{\r
+  CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
+}\r
+\r
 EFI_STATUS\r
 CpuDxeInitialize (\r
   IN EFI_HANDLE         ImageHandle,\r
@@ -239,6 +248,8 @@ CpuDxeInitialize (
 \r
   InitializeExceptions (&mCpu);\r
 \r
+  InitializeDma (&mCpu);\r
+\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                 &mCpuHandle,\r
                 &gEfiCpuArchProtocolGuid,           &mCpu,\r