Missed a fix in the Cpu Driver. Added some more debug for Execption handling and...

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / Mmu.c

diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index 55e049850f6570f0bb03ccea71e673456047cbbe..6d512592c29bc05c2daa82fc3b5153f8ffcf2bbe 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -440,36 +440,37 @@ UpdatePageEntries (
 \r
   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
   // EntryValue: values at bit positions specified by EntryMask\r
-\r
+  EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r
+  EntryValue = ARM_PAGE_TYPE_SMALL;\r
   // Although the PI spec is unclear on this the GCD guarantees that only\r
   // one Attribute bit is set at a time, so we can safely use a switch statement\r
   switch (Attributes) {\r
     case EFI_MEMORY_UC:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // map to strongly ordered\r
-      EntryValue = 0; // TEX[2:0] = 0, C=0, B=0\r
+      EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WC:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // map to normal non-cachable\r
-      EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
+      EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
       break;\r
 \r
     case EFI_MEMORY_WT:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // write through with no-allocate\r
-      EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
+      EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r
       break;\r
 \r
     case EFI_MEMORY_WB:\r
       // modify cacheability attributes\r
-      EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
+      EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r
       // write back (with allocate)\r
-      EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
+      EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r
       break;\r
 \r
     case EFI_MEMORY_WP:\r
@@ -477,8 +478,7 @@ UpdatePageEntries (
     case EFI_MEMORY_UCE:\r
       // cannot be implemented UEFI definition unclear for ARM\r
       // Cause a page fault if these ranges are accessed.\r
-      EntryMask   = 0x3;\r
-      EntryValue = 0;\r
+      EntryValue = ARM_PAGE_TYPE_FAULT;\r
       DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r
       break;\r
 \r
@@ -861,8 +861,9 @@ CpuReconvertPagesPages (
   )\r
 {\r
   EFI_STATUS      Status;\r
-  \r
-  //\r
+DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
+ASSERT (FALSE);\r
+//\r
   // Unmap the alaised Address\r
   //\r
   Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r