#define ARM_PAGE_TYPE_SMALL 0x2\r
#define ARM_PAGE_TYPE_SMALL_XN 0x3\r
\r
-#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)\r
+#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)\r
\r
\r
// Translation Table Base 0 fields\r
UINT32 p;\r
UINT32 PageTableIndex;\r
UINT32 PageTableEntry;\r
+ UINT32 CurrentPageTableEntry;\r
+ VOID *Mva;\r
\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r
\r
+ Status = EFI_SUCCESS;\r
+\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
// EntryValue: values at bit positions specified by EntryMask\r
EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r
\r
// calculate number of 4KB page table entries to change\r
- NumPageEntries = Length/EFI_PAGE_SIZE;\r
+ NumPageEntries = Length/SIZE_4KB;\r
\r
// iterate for the number of 4KB pages to change\r
Offset = 0;\r
ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r
\r
// get the entry\r
- PageTableEntry = PageTable[PageTableIndex];\r
+ CurrentPageTableEntry = PageTable[PageTableIndex];\r
\r
// mask off appropriate fields\r
- PageTableEntry &= ~EntryMask;\r
+ PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r
\r
// mask in new attributes and/or permissions\r
PageTableEntry |= EntryValue;\r
// Make this virtual address point at a physical page\r
PageTableEntry &= ~VirtualMask;\r
}\r
- \r
- // update the entry\r
- PageTable[PageTableIndex] = PageTableEntry; \r
\r
+ if (CurrentPageTableEntry != PageTableEntry) {\r
+ Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));\r
+ if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {\r
+ // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r
+ // Note assumes switch(Attributes), not ARMv7 possibilities\r
+ WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r
+ }\r
+\r
+ // Only need to update if we are changing the entry \r
+ PageTable[PageTableIndex] = PageTableEntry; \r
+ ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r
+ }\r
\r
Status = EFI_SUCCESS;\r
- Offset += EFI_PAGE_SIZE;\r
+ Offset += SIZE_4KB;\r
\r
} // end first level translation table loop\r
\r
UINT32 FirstLevelIdx;\r
UINT32 NumSections;\r
UINT32 i;\r
+ UINT32 CurrentDescriptor;\r
UINT32 Descriptor;\r
-\r
+ VOID *Mva;\r
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r
\r
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r
switch(Attributes) {\r
case EFI_MEMORY_UC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// map to strongly ordered\r
EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r
break;\r
\r
case EFI_MEMORY_WC:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// map to normal non-cachable\r
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
case EFI_MEMORY_WT:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// write through with no-allocate\r
EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r
break;\r
\r
case EFI_MEMORY_WB:\r
// modify cacheability attributes\r
- EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;\r
+ EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r
// write back (with allocate)\r
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r
break;\r
\r
// iterate through each descriptor\r
for(i=0; i<NumSections; i++) {\r
- Descriptor = FirstLevelTable[FirstLevelIdx + i];\r
+ CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
// has this descriptor already been coverted to pages?\r
- if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
+ if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r
// forward this 1MB range to page table function instead\r
Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r
} else {\r
// still a section entry\r
\r
// mask off appropriate fields\r
- Descriptor &= ~EntryMask;\r
+ Descriptor = CurrentDescriptor & ~EntryMask;\r
\r
// mask in new attributes and/or permissions\r
Descriptor |= EntryValue;\r
Descriptor &= ~VirtualMask;\r
}\r
\r
- FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+ if (CurrentDescriptor != Descriptor) {\r
+ Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);\r
+ if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {\r
+ // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r
+ // Note assumes switch(Attributes), not ARMv7 possabilities\r
+ WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r
+ }\r
+\r
+ // Only need to update if we are changing the descriptor \r
+ FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r
+ ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r
+ }\r
\r
Status = EFI_SUCCESS;\r
}\r
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r
\r
// write the page table entries out\r
- for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {\r
+ for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {\r
PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r
}\r
\r
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r
- InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);\r
+ WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r
\r
// formulate page table entry, Domain=0, NS=0\r
PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r
)\r
{\r
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r
- if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){\r
- // minimum granularity is EFI_PAGE_SIZE (4KB on ARM)\r
- DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));\r
+ if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r
+ // minimum granularity is SIZE_4KB (4KB on ARM)\r
+ DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r
return EFI_UNSUPPORTED;\r
}\r
\r
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r
}\r
\r
+ DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));\r
+\r
return Status;\r
}\r
\r
\r
EFI_STATUS\r
EFIAPI\r
-CpuReconvertPagesPages (\r
+CpuReconvertPages (\r
IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r
IN EFI_PHYSICAL_ADDRESS Address,\r
IN UINTN Length,\r
)\r
{\r
EFI_STATUS Status;\r
-DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
-ASSERT (FALSE);\r
-//\r
+\r
+ DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r
+ \r
+ //\r
// Unmap the alaised Address\r
//\r
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r
\r
VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r
CpuConvertPagesToUncachedVirtualAddress,\r
- CpuReconvertPagesPages\r
+ CpuReconvertPages\r
};\r
\r
\r
projects / mirror_edk2.git / blobdiff