#define MCI_STATUS_CMD_DATACRCFAIL 0x2\r
#define MCI_STATUS_CMD_CMDTIMEOUT 0x4\r
#define MCI_STATUS_CMD_DATATIMEOUT 0x8\r
+#define MCI_STATUS_CMD_TX_UNDERRUN 0x10\r
#define MCI_STATUS_CMD_RXOVERRUN 0x20\r
#define MCI_STATUS_CMD_RESPEND 0x40\r
#define MCI_STATUS_CMD_SENT 0x80\r
#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end\r
+#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200\r
#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end\r
#define MCI_STATUS_CMD_ACTIVE 0x800\r
#define MCI_STATUS_CMD_RXACTIVE (1 << 13)\r
#define MCI_DATACTL_CARD_TO_CONT 2\r
#define MCI_DATACTL_BLOCK_TRANS 0\r
#define MCI_DATACTL_STREAM_TRANS 4\r
-#define MCI_DATACTL_DMA_ENABLE 8\r
+#define MCI_DATACTL_DMA_ENABLE (1 << 3)\r
\r
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) | MCI_CPSM_ENABLED)\r
\r