ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code

[mirror_edk2.git] / ArmPkg / Drivers / PL310L2Cache / PL310L2Cache.c

diff --git a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
index ea03097ef28f3bf277ebfa9cbfe50c0c0f390a38..b701978da59ae8041128e033fd0d8603857ceb02 100644 (file)
--- a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
+++ b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
@@ -15,7 +15,7 @@
 #include <Library/IoLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/ArmLib.h>\r
-#include <Library/L2X0CacheLib.h>\r
+#include <Drivers/PL310L2Cache.h>\r
 #include <Library/PcdLib.h>\r
 \r
 #define L2x0WriteReg(reg,val)               MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r
@@ -25,6 +25,10 @@
 VOID\r
 L2x0CacheInit (\r
   IN  UINTN   L2x0Base,\r
+  IN  UINT32  L2x0TagLatencies,\r
+  IN  UINT32  L2x0DataLatencies,\r
+  IN  UINT32  L2x0AuxValue,\r
+  IN  UINT32  L2x0AuxMask,\r
   IN  BOOLEAN CacheEnabled\r
   )\r
 {\r
@@ -66,9 +70,9 @@ L2x0CacheInit (
   Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
   // Use default Size\r
   Data = L2x0ReadReg(L2X0_AUXCTRL);\r
-  Aux |= Data & (0x7 << 17);\r
+  Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;\r
   // Use default associativity\r
-  Aux |= Data & (0x1 << 16);\r
+  Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;\r
   // Enabled I & D Prefetch\r
   Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
 \r
@@ -88,29 +92,16 @@ L2x0CacheInit (
     L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
   }\r
 \r
-    if (Revision >= 4) {\r
-        // Tag RAM Latency register\r
-        // - Use default latency\r
-    \r
-        // Data RAM Latency Control register\r
-        // - Use default latency\r
-    } else if (Revision >= 2) {\r
-        L2x0WriteReg(L230_TAG_LATENCY,\r
-            (L2_TAG_ACCESS_LATENCY << 8)\r
-            | (L2_TAG_ACCESS_LATENCY << 4)\r
-            | L2_TAG_SETUP_LATENCY\r
-        );\r
-        \r
-        L2x0WriteReg(L230_DATA_LATENCY,\r
-            (L2_DATA_ACCESS_LATENCY << 8)\r
-            | (L2_DATA_ACCESS_LATENCY << 4)\r
-            | L2_DATA_SETUP_LATENCY\r
-        );\r
-    } else {\r
-        Aux |= (L2_TAG_ACCESS_LATENCY << 6)\r
-               | (L2_DATA_ACCESS_LATENCY << 3)\r
-               | L2_DATA_ACCESS_LATENCY;\r
-    }\r
+  if (Revision >= 2) {\r
+    L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);\r
+    L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);\r
+  } else {\r
+    // PL310 old style latency is not supported yet\r
+    ASSERT(0);\r
+  }\r
+\r
+  // Set the platform specific values\r
+  Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;\r
 \r
   // Write Auxiliary value\r
   L2x0WriteReg(L2X0_AUXCTRL, Aux);\r