ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11735 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
index ea03097ef28f3bf277ebfa9cbfe50c0c0f390a38..b701978da59ae8041128e033fd0d8603857ceb02 100644 (file)
--- a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
+++ b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
@@ -15,7 +15,7 @@
 #include <Library/IoLib.h>\r
 #include <Library/DebugLib.h>\r
 #include <Library/ArmLib.h>\r
-#include <Library/L2X0CacheLib.h>\r
+#include <Drivers/PL310L2Cache.h>\r
 #include <Library/PcdLib.h>\r
 \r
 #define L2x0WriteReg(reg,val)               MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r
@@ -25,6 +25,10 @@
 VOID\r
 L2x0CacheInit (\r
   IN  UINTN   L2x0Base,\r
+  IN  UINT32  L2x0TagLatencies,\r
+  IN  UINT32  L2x0DataLatencies,\r
+  IN  UINT32  L2x0AuxValue,\r
+  IN  UINT32  L2x0AuxMask,\r
   IN  BOOLEAN CacheEnabled\r
   )\r
 {\r
@@ -66,9 +70,9 @@ L2x0CacheInit (
   Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
   // Use default Size\r
   Data = L2x0ReadReg(L2X0_AUXCTRL);\r
-  Aux |= Data & (0x7 << 17);\r
+  Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;\r
   // Use default associativity\r
-  Aux |= Data & (0x1 << 16);\r
+  Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;\r
   // Enabled I & D Prefetch\r
   Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
 \r
@@ -88,29 +92,16 @@ L2x0CacheInit (
     L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
   }\r
 \r
-    if (Revision >= 4) {\r
-        // Tag RAM Latency register\r
-        // - Use default latency\r
-    \r
-        // Data RAM Latency Control register\r
-        // - Use default latency\r
-    } else if (Revision >= 2) {\r
-        L2x0WriteReg(L230_TAG_LATENCY,\r
-            (L2_TAG_ACCESS_LATENCY << 8)\r
-            | (L2_TAG_ACCESS_LATENCY << 4)\r
-            | L2_TAG_SETUP_LATENCY\r
-        );\r
-        \r
-        L2x0WriteReg(L230_DATA_LATENCY,\r
-            (L2_DATA_ACCESS_LATENCY << 8)\r
-            | (L2_DATA_ACCESS_LATENCY << 4)\r
-            | L2_DATA_SETUP_LATENCY\r
-        );\r
-    } else {\r
-        Aux |= (L2_TAG_ACCESS_LATENCY << 6)\r
-               | (L2_DATA_ACCESS_LATENCY << 3)\r
-               | L2_DATA_ACCESS_LATENCY;\r
-    }\r
+  if (Revision >= 2) {\r
+    L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);\r
+    L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);\r
+  } else {\r
+    // PL310 old style latency is not supported yet\r
+    ASSERT(0);\r
+  }\r
+\r
+  // Set the platform specific values\r
+  Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;\r
 \r
   // Write Auxiliary value\r
   L2x0WriteReg(L2X0_AUXCTRL, Aux);\r

diff --git a/ArmPkg/Include/Drivers/PL310L2Cache.h b/ArmPkg/Include/Drivers/PL310L2Cache.h
new file mode 100644 (file)
index 0000000..a610998
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL310L2Cache.h
@@ -0,0 +1,79 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef L2CACHELIB_H_\r
+#define L2CACHELIB_H_\r
+\r
+#define L2X0_CACHEID            0x000\r
+#define L2X0_CTRL               0x100\r
+#define L2X0_AUXCTRL            0x104\r
+#define L230_TAG_LATENCY        0x108\r
+#define L230_DATA_LATENCY       0x10C\r
+#define L2X0_INTCLEAR           0x220\r
+#define L2X0_CACHE_SYNC         0x730\r
+#define L2X0_INVWAY             0x77C\r
+#define L2X0_CLEAN_WAY          0x7BC\r
+#define L2X0_PFCTRL             0xF60\r
+#define L2X0_PWRCTRL            0xF80\r
+\r
+#define L2X0_CACHEID_IMPLEMENTER_ARM        0x41\r
+#define L2X0_CACHEID_PARTNUM_PL310          0x03\r
+\r
+#define L2X0_CTRL_ENABLED                   0x1\r
+#define L2X0_CTRL_DISABLED                  0x0\r
+\r
+#define L2X0_AUXCTRL_EXCLUSIVE              (1 << 12)\r
+#define L2X0_AUXCTRL_ASSOCIATIVITY          (1 << 16)\r
+#define L2X0_AUXCTRL_WAYSIZE_MASK           (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_16KB           (1 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_32KB           (2 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_64KB           (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_128KB          (4 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_256KB          (5 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_512KB          (6 << 17)\r
+#define L2X0_AUXCTRL_EM                     (1 << 20)\r
+#define L2X0_AUXCTRL_SHARED_OVERRIDE        (1 << 22)\r
+#define L2x0_AUXCTRL_AW_AWCACHE             (0 << 23)\r
+#define L2x0_AUXCTRL_AW_NOALLOC             (1 << 23)\r
+#define L2x0_AUXCTRL_AW_OVERRIDE            (2 << 23)\r
+#define L2X0_AUXCTRL_SBO                    (1 << 25)\r
+#define L2X0_AUXCTRL_NSAC                   (1 << 27)\r
+#define L2x0_AUXCTRL_DPREFETCH              (1 << 28)\r
+#define L2x0_AUXCTRL_IPREFETCH              (1 << 29)\r
+#define L2x0_AUXCTRL_EARLY_BRESP            (1 << 30)\r
+\r
+#define L2x0_LATENCY_1_CYCLE                 0\r
+#define L2x0_LATENCY_2_CYCLES                1\r
+#define L2x0_LATENCY_3_CYCLES                2\r
+#define L2x0_LATENCY_4_CYCLES                3\r
+#define L2x0_LATENCY_5_CYCLES                4\r
+#define L2x0_LATENCY_6_CYCLES                5\r
+#define L2x0_LATENCY_7_CYCLES                6\r
+#define L2x0_LATENCY_8_CYCLES                7\r
+\r
+#define PL310_LATENCIES(Write,Read,Setup)      (((Write) << 8) | ((Read) << 4) | (Setup))\r
+#define PL310_TAG_LATENCIES(Write,Read,Setup)  PL310_LATENCIES(Write,Read,Setup)\r
+#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
+\r
+VOID\r
+L2x0CacheInit (\r
+  IN  UINTN   L2x0Base,\r
+  IN  UINT32  L2x0TagLatencies,\r
+  IN  UINT32  L2x0DataLatencies,\r
+  IN  UINT32  L2x0AuxValue,\r
+  IN  UINT32  L2x0AuxMask,\r
+  IN  BOOLEAN CacheEnabled\r
+  );\r
+\r
+#endif /* L2CACHELIB_H_ */\r

diff --git a/ArmPkg/Include/Library/L2X0CacheLib.h b/ArmPkg/Include/Library/L2X0CacheLib.h
deleted file mode 100644 (file)
index 69754e4..0000000
--- a/ArmPkg/Include/Library/L2X0CacheLib.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** @file\r
-*\r
-*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-*  This program and the accompanying materials\r
-*  are licensed and made available under the terms and conditions of the BSD License\r
-*  which accompanies this distribution.  The full text of the license may be found at\r
-*  http://opensource.org/licenses/bsd-license.php\r
-*\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef L2CACHELIB_H_\r
-#define L2CACHELIB_H_\r
-\r
-#define L2_LATENCY                          7\r
-\r
-#define L2_TAG_ACCESS_LATENCY               L2_LATENCY\r
-#define L2_TAG_SETUP_LATENCY                L2_LATENCY\r
-#define L2_DATA_ACCESS_LATENCY              L2_LATENCY\r
-#define L2_DATA_SETUP_LATENCY               L2_LATENCY\r
-\r
-\r
-#define L2X0_CACHEID            0x000\r
-#define L2X0_CTRL               0x100\r
-#define L2X0_AUXCTRL            0x104\r
-#define L230_TAG_LATENCY        0x108\r
-#define L230_DATA_LATENCY       0x10C\r
-#define L2X0_INTCLEAR           0x220\r
-#define L2X0_CACHE_SYNC      0x730\r
-#define L2X0_INVWAY             0x77C\r
-#define L2X0_CLEAN_WAY          0x7BC\r
-#define L2X0_PFCTRL             0xF60\r
-#define L2X0_PWRCTRL            0xF80\r
-\r
-#define L2X0_CACHEID_IMPLEMENTER_ARM        0x41\r
-#define L2X0_CACHEID_PARTNUM_PL310          0x03\r
-\r
-#define L2X0_CTRL_ENABLED                   0x1\r
-#define L2X0_CTRL_DISABLED                  0x0\r
-\r
-#define L2X0_AUXCTRL_EXCLUSIVE              (1<<12)\r
-#define L2X0_AUXCTRL_WAYSIZE_16KB           (0x001 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_32KB           (0x010 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_64KB           (0x011 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_128KB          (0x100 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_256KB          (0x101 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_512KB          (0x110 << 17)\r
-#define L2X0_AUXCTRL_EM                     (1 << 20)\r
-#define L2x0_AUXCTRL_AW_AWCACHE             (0x00 << 23)\r
-#define L2x0_AUXCTRL_AW_NOALLOC             (0x01 << 23)\r
-#define L2x0_AUXCTRL_AW_OVERRIDE            (0x10 << 23)\r
-#define L2X0_AUXCTRL_SBO                    (1 << 25)\r
-#define L2X0_AUXCTRL_NSAC                   (1 << 27)\r
-#define L2x0_AUXCTRL_DPREFETCH              (1 << 28)\r
-#define L2x0_AUXCTRL_IPREFETCH              (1 << 29)\r
-\r
-VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);\r
-\r
-#endif /* L2CACHELIB_H_ */\r

diff --git a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
index 6193cb6132a2aef3a5c5d234e2d37141d35ac2d0..ec0a0dd4645ae68ef5cd3ec5e7537014e80a2b0a 100644 (file)
--- a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
+++ b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
@@ -12,12 +12,17 @@
 *\r
 **/\r
 \r
-#include <Library/L2X0CacheLib.h>\r
+#include <Uefi.h>\r
+#include <Drivers/PL310L2Cache.h>\r
 \r
 // Initialize L2X0 Cache Controller\r
 VOID\r
 L2x0CacheInit (\r
   IN  UINTN   L2x0Base,\r
+  IN  UINT32  L2x0TagLatencies,\r
+  IN  UINT32  L2x0DataLatencies,\r
+  IN  UINT32  L2x0AuxValue,\r
+  IN  UINT32  L2x0AuxMask,\r
   IN  BOOLEAN CacheEnabled\r
   )\r
 {\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
index 82b4ae14cb63f4eba95f595f1afd5a99aa38ec47..b8d1ff0f722f33330c83e3b0a5ae4b1d888ff1c4 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
@@ -19,7 +19,7 @@
 #include <Library/PcdLib.h>
 #include <Drivers/PL341Dmc.h>
 #include <Drivers/PL301Axi.h>
-#include <Library/L2X0CacheLib.h>
+#include <Drivers/PL310L2Cache.h>
 #include <Library/SerialPortLib.h>
 
 #define SerialPrint(txt)  SerialPortWrite (txt, AsciiStrLen(txt)+1);
@@ -186,7 +186,11 @@ ArmPlatformSecInitialize (
   VOID
   ) {
   // The L2x0 controller must be intialize in Secure World
-  L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE);
+  L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
+      PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
+      PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
+      0,~0, // Use default setting for the Auxiliary Control Register
+      FALSE);
 }
 
 /**