ArmDisableFiq ();\r
\r
if (FeaturePcdGet(PcdRelocateVectorTable) == TRUE) {\r
- //\r
- // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.\r
- //\r
- Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r
- \r
- //\r
- // Reserve space for the exception handlers\r
- //\r
- Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);\r
- VectorBase = (UINT32 *)(UINTN)Base;\r
- Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);\r
- // If the request was for memory that's not in the memory map (which is often the case for 0x00000000\r
- // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of \r
- // EFI_NOT_FOUND, and continue in that case.\r
- if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
- \r
+ //\r
+ // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.\r
+ //\r
+ Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r
+\r
+ //\r
+ // Reserve space for the exception handlers\r
+ //\r
+ Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);\r
+ VectorBase = (UINT32 *)(UINTN)Base;\r
+ Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);\r
+ // If the request was for memory that's not in the memory map (which is often the case for 0x00000000\r
+ // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of\r
+ // EFI_NOT_FOUND, and continue in that case.\r
+ if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {\r
// Save existing vector table, in case debugger is already hooked in\r
CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (gDebuggerExceptionHandlers));\r
}\r
- \r
- // Copy our assembly code into the page that contains the exception vectors. \r
- CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);\r
- \r
- //\r
- // Patch in the common Assembly exception handler\r
- //\r
- Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;\r
- *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;\r
- \r
- //\r
- // Initialize the C entry points for interrupts\r
- //\r
- for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {\r
+\r
+ // Copy our assembly code into the page that contains the exception vectors.\r
+ CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);\r
+\r
+ //\r
+ // Patch in the common Assembly exception handler\r
+ //\r
+ Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;\r
+ *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;\r
+\r
+ //\r
+ // Initialize the C entry points for interrupts\r
+ //\r
+ for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {\r
if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||\r
(gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)(UINTN)0xEAFFFFFE)) {\r
- // Exception handler contains branch to vector location (jmp $) so no handler\r
- // NOTE: This code assumes vectors are ARM and not Thumb code\r
- Status = RegisterInterruptHandler (Index, NULL);\r
- ASSERT_EFI_ERROR (Status);\r
- } else {\r
- // If the debugger has alread hooked put its vector back\r
- VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];\r
- }\r
+ // Exception handler contains branch to vector location (jmp $) so no handler\r
+ // NOTE: This code assumes vectors are ARM and not Thumb code\r
+ Status = RegisterInterruptHandler (Index, NULL);\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
+ // If the debugger has already hooked put its vector back\r
+ VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];\r
}\r
- \r
- // Flush Caches since we updated executable stuff\r
- InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);\r
+ }\r
+\r
+ // Flush Caches since we updated executable stuff\r
+ InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);\r
\r
- //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.\r
- // The Vector Base Address Register defines the location\r
- ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));\r
+ //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.\r
+ // The Vector Base Address Register defines the location\r
+ ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));\r
} else {\r
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.\r
ArmWriteVBar((UINT32)ExceptionHandlersStart);\r
#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)\r
\r
// Initialize PL320 L2 Cache Controller\r
-VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {\r
- UINT32 Data;\r
- UINT32 Revision;\r
- UINT32 Aux;\r
- UINT32 PfCtl;\r
- UINT32 PwrCtl;\r
-\r
- // Check if L2x0 is present and is an ARM implementation\r
- Data = L2x0ReadReg(L2X0_CACHEID);\r
- if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // Check if L2x0 is PL310\r
- if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // RTL release\r
- Revision = Data & 0x3F;\r
-\r
- // Check if L2x0 is already enabled then we disable it\r
- Data = L2x0ReadReg(L2X0_CTRL);\r
- if (Data & L2X0_CTRL_ENABLED) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r
- }\r
-\r
- //\r
- // Set up global configurations\r
- //\r
-\r
- // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r
- Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r
- // Use AWCACHE attributes for WA\r
- Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
- // Use default Size\r
- Data = L2x0ReadReg(L2X0_AUXCTRL);\r
- Aux |= Data & (0x7 << 17);\r
- // Use default associativity\r
- Aux |= Data & (0x1 << 16);\r
- // Enabled I & D Prefetch\r
- Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
- \r
- if (Revision >= 5) {\r
- // Prefetch Offset Register\r
- PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r
- // - Prefetch increment set to 0\r
- // - Prefetch dropping off\r
- // - Double linefills off\r
- L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r
-\r
- // Power Control Register - L2X0_PWRCTRL\r
- PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r
- // - Standby when idle off\r
- // - Dynamic clock gating off\r
- // - Nc,NC-shared dropping off\r
- L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
- }\r
+VOID\r
+L2x0CacheInit (\r
+ IN UINTN L2x0Base,\r
+ IN BOOLEAN CacheEnabled\r
+ )\r
+{\r
+ UINT32 Data;\r
+ UINT32 Revision;\r
+ UINT32 Aux;\r
+ UINT32 PfCtl;\r
+ UINT32 PwrCtl;\r
+\r
+ // Check if L2x0 is present and is an ARM implementation\r
+ Data = L2x0ReadReg(L2X0_CACHEID);\r
+ if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r
+ ASSERT(0);\r
+ return;\r
+ }\r
+\r
+ // Check if L2x0 is PL310\r
+ if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r
+ ASSERT(0);\r
+ return;\r
+ }\r
+\r
+ // RTL release\r
+ Revision = Data & 0x3F;\r
+\r
+ // Check if L2x0 is already enabled then we disable it\r
+ Data = L2x0ReadReg(L2X0_CTRL);\r
+ if (Data & L2X0_CTRL_ENABLED) {\r
+ L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r
+ }\r
+\r
+ //\r
+ // Set up global configurations\r
+ //\r
+\r
+ // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r
+ Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r
+ // Use AWCACHE attributes for WA\r
+ Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
+ // Use default Size\r
+ Data = L2x0ReadReg(L2X0_AUXCTRL);\r
+ Aux |= Data & (0x7 << 17);\r
+ // Use default associativity\r
+ Aux |= Data & (0x1 << 16);\r
+ // Enabled I & D Prefetch\r
+ Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
+\r
+ if (Revision >= 5) {\r
+ // Prefetch Offset Register\r
+ PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r
+ // - Prefetch increment set to 0\r
+ // - Prefetch dropping off\r
+ // - Double linefills off\r
+ L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r
+\r
+ // Power Control Register - L2X0_PWRCTRL\r
+ PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r
+ // - Standby when idle off\r
+ // - Dynamic clock gating off\r
+ // - Nc,NC-shared dropping off\r
+ L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
+ }\r
\r
if (Revision >= 4) {\r
// Tag RAM Latency register\r
| L2_DATA_ACCESS_LATENCY;\r
}\r
\r
- // Write Auxiliary value\r
- L2x0WriteReg(L2X0_AUXCTRL, Aux);\r
+ // Write Auxiliary value\r
+ L2x0WriteReg(L2X0_AUXCTRL, Aux);\r
\r
- //\r
- // Invalidate all entries in cache\r
- //\r
- L2x0WriteReg(L2X0_INVWAY, 0xffff);\r
- // Poll cache maintenance register until invalidate operation is complete\r
- while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r
+ //\r
+ // Invalidate all entries in cache\r
+ //\r
+ L2x0WriteReg(L2X0_INVWAY, 0xffff);\r
+ // Poll cache maintenance register until invalidate operation is complete\r
+ while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r
\r
- // Write to the Lockdown D and Lockdown I Register 9 if required\r
- // - Not required\r
+ // Write to the Lockdown D and Lockdown I Register 9 if required\r
+ // - Not required\r
\r
- // Clear any residual raw interrupts\r
- L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r
+ // Clear any residual raw interrupts\r
+ L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r
\r
- // Enable the cache\r
- if (CacheEnabled) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r
- }\r
+ // Enable the cache\r
+ if (CacheEnabled) {\r
+ L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r
+ }\r
}\r
scu_base = ArmGetScuBaseAddress();
- /* Invalidate all: write -1 to SCU Invalidate All register */
+ // Invalidate all: write -1 to SCU Invalidate All register
MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff);
- /* Enable SCU */
+ // Enable SCU
MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1);
}
bx lr
ASM_PFX(ArmEnableVFP):
- // Enable VFP registers
+ # Enable VFP registers
mrc p15, 0, r0, c1, c0, 2
- orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
+ orr r0, r0, #0x00f00000 @ Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
- mov r0, #0x40000000 // Set EN bit in FPEXC
- mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
+ mov r0, #0x40000000 @ Set EN bit in FPEXC
+ mcr p10,#0x7,r0,c8,c0,#0 @ msr FPEXC,r0 in ARM assembly
bx lr
ASM_PFX(ArmCallWFI):
wfi
bx lr
-//Note: Return 0 in Uniprocessor implementation
+#Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar):
- mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
+ mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
\r
-VOID ArmClearMPCoreMailbox() {\r
+VOID\r
+ArmClearMPCoreMailbox (\r
+ VOID\r
+ )\r
+{\r
MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));\r
}\r
\r
-UINTN ArmGetMPCoreMailbox() {\r
- return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));\r
+UINTN\r
+ArmGetMPCoreMailbox (\r
+ VOID\r
+ )\r
+{\r
+ return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));\r
}\r
#include <Library/L2X0CacheLib.h>\r
\r
// Initialize L2X0 Cache Controller\r
-VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {\r
+VOID\r
+L2x0CacheInit (\r
+ IN UINTN L2x0Base,\r
+ IN BOOLEAN CacheEnabled\r
+ )\r
+{\r
//No implementation\r
}\r
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