ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native mode

[mirror_edk2.git] / ArmPkg / Include / AsmMacroIoLibV8.h

diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacroIoLibV8.h
index 5ab1b5723eb866fa6c796391a4c44a481edbf33b..2ee1081632bafd1be1352d179e6c841ae21672c9 100644 (file)
--- a/ArmPkg/Include/AsmMacroIoLibV8.h
+++ b/ArmPkg/Include/AsmMacroIoLibV8.h
@@ -1,5 +1,5 @@
 /** @file\r
-  Macros to work around lack of Apple support for LDR register, =expr\r
+  Macros to work around lack of Clang support for LDR register, =expr\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
@@ -18,54 +18,6 @@
 #ifndef __MACRO_IO_LIBV8_H__\r
 #define __MACRO_IO_LIBV8_H__\r
 \r
-#if defined (__GNUC__)\r
-\r
-#define MmioWrite32(Address, Data) \\r
-  ldr  x1, =Address ;              \\r
-  ldr  w0, =Data    ;              \\r
-  str  w0, [x1]\r
-\r
-#define MmioOr32(Address, OrData) \\r
-  ldr  x1, =Address ;             \\r
-  ldr  w2, =OrData  ;             \\r
-  ldr  w0, [x1]     ;             \\r
-  orr  w0, w0, w2   ;             \\r
-  str  w0, [x1]\r
-\r
-#define MmioAnd32(Address, AndData) \\r
-  ldr  x1, =Address ;               \\r
-  ldr  w2, =AndData ;               \\r
-  ldr  w0, [x1]     ;               \\r
-  and  w0, w0, w2   ;               \\r
-  str  w0, [x1]\r
-\r
-#define MmioAndThenOr32(Address, AndData, OrData) \\r
-  ldr  x1, =Address ;                             \\r
-  ldr  w0, [x1]     ;                             \\r
-  ldr  w2, =AndData ;                             \\r
-  and  w0, w0, w2   ;                             \\r
-  ldr  w2, =OrData  ;                             \\r
-  orr  w0, w0, w2   ;                             \\r
-  str  w0, [x1]\r
-\r
-#define MmioWriteFromReg32(Address, Reg) \\r
-  ldr  x1, =Address ;                    \\r
-  str  Reg, [x1]\r
-\r
-#define MmioRead32(Address) \\r
-  ldr  x1, =Address ;       \\r
-  ldr  w0, [x1]\r
-\r
-#define MmioReadToReg32(Address, Reg) \\r
-  ldr  x1, =Address ;                 \\r
-  ldr  Reg, [x1]\r
-\r
-#define LoadConstant(Data) \\r
-  ldr  x0, =Data\r
-\r
-#define LoadConstantToReg(Data, Reg) \\r
-  ldr  Reg, =Data\r
-\r
 #define SetPrimaryStack(StackTop, GlobalSize, Tmp, Tmp1)  \\r
   ands    Tmp, GlobalSize, #15        ;                   \\r
   mov     Tmp1, #16                   ;                   \\r
@@ -124,12 +76,35 @@ _InitializePrimaryStackEnd:
         cmp    SAFE_XREG, #0x4      ;\\r
         b.ne   .                    ;// We should never get here\r
 // EL1 code starts here\r
+#if defined(__clang__)\r
+\r
+// load x0 with _Data\r
+#define LoadConstant(_Data)              \\r
+  ldr  x0, 1f                          ; \\r
+  b    2f                              ; \\r
+.align(8)                              ; \\r
+1:                                       \\r
+  .8byte (_Data)                       ; \\r
+2:\r
+\r
+// load _Reg with _Data\r
+#define LoadConstantToReg(_Data, _Reg)    \\r
+  ldr  _Reg, 1f                         ; \\r
+  b    2f                               ; \\r
+.align(8)                               ; \\r
+1:                                        \\r
+  .8byte (_Data)                        ; \\r
+2:\r
+\r
+#elif defined (__GNUC__)\r
 \r
-#else\r
+#define LoadConstant(Data) \\r
+  ldr  x0, =Data\r
 \r
-#error RVCT AArch64 tool chain is not supported\r
+#define LoadConstantToReg(Data, Reg) \\r
+  ldr  Reg, =Data\r
 \r
-#endif // __GNUC__ \r
+#endif // __GNUC__\r
 \r
 #endif // __MACRO_IO_LIBV8_H__\r
 \r