ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Include / Chipset / ArmV7.h

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 909686ce361abda8f42cf2a53fb341691b2c0a47..ceb32170eda60619f2deba668bd4a7f8d89c47e2 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -17,6 +17,15 @@
 #define __ARM_V7_H__\r
 \r
 #include <Chipset/ArmV7Mmu.h>\r
+#include <Chipset/ArmArchTimer.h>\r
+\r
+// ARM Interrupt ID in Exception Table\r
+#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ\r
+\r
+// ID_PFR1 - ARM Processor Feature Register 1 definitions\r
+#define ARM_PFR1_SEC        (0xFUL << 4)\r
+#define ARM_PFR1_TIMER      (0xFUL << 16)\r
+#define ARM_PFR1_GIC        (0xFUL << 28)\r
 \r
 // Domain Access Control Register\r
 #define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))\r
@@ -25,6 +34,21 @@
 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
 \r
+// CPSR - Coprocessor Status Register definitions\r
+#define CPSR_MODE_USER       0x10\r
+#define CPSR_MODE_FIQ        0x11\r
+#define CPSR_MODE_IRQ        0x12\r
+#define CPSR_MODE_SVC        0x13\r
+#define CPSR_MODE_ABORT      0x17\r
+#define CPSR_MODE_HYP        0x1A\r
+#define CPSR_MODE_UNDEFINED  0x1B\r
+#define CPSR_MODE_SYSTEM     0x1F\r
+#define CPSR_MODE_MASK       0x1F\r
+#define CPSR_ASYNC_ABORT     (1 << 8)\r
+#define CPSR_IRQ             (1 << 7)\r
+#define CPSR_FIQ             (1 << 6)\r
+\r
+\r
 // CPACR - Coprocessor Access Control Register definitions\r
 #define CPACR_CP_DENIED(cp)     0x00\r
 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r
@@ -52,17 +76,25 @@
 \r
 // MIDR - Main ID Register definitions\r
 #define ARM_CPU_TYPE_MASK       0xFFF\r
+#define ARM_CPU_TYPE_AEMv8      0xD0F\r
+#define ARM_CPU_TYPE_A53        0xD03\r
+#define ARM_CPU_TYPE_A57        0xD07\r
 #define ARM_CPU_TYPE_A15        0xC0F\r
 #define ARM_CPU_TYPE_A9         0xC09\r
 #define ARM_CPU_TYPE_A5         0xC05\r
 \r
+#define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
+\r
 VOID\r
 EFIAPI\r
 ArmEnableSWPInstruction (\r
   VOID\r
   );\r
 \r
-UINTN \r
+UINTN\r
 EFIAPI\r
 ArmReadCbar (\r
   VOID\r
@@ -80,10 +112,16 @@ ArmWriteTpidrurw (
   UINTN Value\r
   );\r
 \r
-UINTN\r
+UINT32\r
 EFIAPI\r
-ArmReadIdPfr1 (\r
+ArmReadNsacr (\r
   VOID\r
   );\r
-  \r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteNsacr (\r
+  IN  UINT32   Nsacr\r
+  );\r
+\r
 #endif // __ARM_V7_H__\r