ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code

[mirror_edk2.git] / ArmPkg / Include / Drivers / PL310L2Cache.h

diff --git a/ArmPkg/Include/Drivers/PL310L2Cache.h b/ArmPkg/Include/Drivers/PL310L2Cache.h
new file mode 100644 (file)
index 0000000..a610998
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL310L2Cache.h
@@ -0,0 +1,79 @@
+/** @file\r
+*\r
+*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef L2CACHELIB_H_\r
+#define L2CACHELIB_H_\r
+\r
+#define L2X0_CACHEID            0x000\r
+#define L2X0_CTRL               0x100\r
+#define L2X0_AUXCTRL            0x104\r
+#define L230_TAG_LATENCY        0x108\r
+#define L230_DATA_LATENCY       0x10C\r
+#define L2X0_INTCLEAR           0x220\r
+#define L2X0_CACHE_SYNC         0x730\r
+#define L2X0_INVWAY             0x77C\r
+#define L2X0_CLEAN_WAY          0x7BC\r
+#define L2X0_PFCTRL             0xF60\r
+#define L2X0_PWRCTRL            0xF80\r
+\r
+#define L2X0_CACHEID_IMPLEMENTER_ARM        0x41\r
+#define L2X0_CACHEID_PARTNUM_PL310          0x03\r
+\r
+#define L2X0_CTRL_ENABLED                   0x1\r
+#define L2X0_CTRL_DISABLED                  0x0\r
+\r
+#define L2X0_AUXCTRL_EXCLUSIVE              (1 << 12)\r
+#define L2X0_AUXCTRL_ASSOCIATIVITY          (1 << 16)\r
+#define L2X0_AUXCTRL_WAYSIZE_MASK           (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_16KB           (1 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_32KB           (2 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_64KB           (3 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_128KB          (4 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_256KB          (5 << 17)\r
+#define L2X0_AUXCTRL_WAYSIZE_512KB          (6 << 17)\r
+#define L2X0_AUXCTRL_EM                     (1 << 20)\r
+#define L2X0_AUXCTRL_SHARED_OVERRIDE        (1 << 22)\r
+#define L2x0_AUXCTRL_AW_AWCACHE             (0 << 23)\r
+#define L2x0_AUXCTRL_AW_NOALLOC             (1 << 23)\r
+#define L2x0_AUXCTRL_AW_OVERRIDE            (2 << 23)\r
+#define L2X0_AUXCTRL_SBO                    (1 << 25)\r
+#define L2X0_AUXCTRL_NSAC                   (1 << 27)\r
+#define L2x0_AUXCTRL_DPREFETCH              (1 << 28)\r
+#define L2x0_AUXCTRL_IPREFETCH              (1 << 29)\r
+#define L2x0_AUXCTRL_EARLY_BRESP            (1 << 30)\r
+\r
+#define L2x0_LATENCY_1_CYCLE                 0\r
+#define L2x0_LATENCY_2_CYCLES                1\r
+#define L2x0_LATENCY_3_CYCLES                2\r
+#define L2x0_LATENCY_4_CYCLES                3\r
+#define L2x0_LATENCY_5_CYCLES                4\r
+#define L2x0_LATENCY_6_CYCLES                5\r
+#define L2x0_LATENCY_7_CYCLES                6\r
+#define L2x0_LATENCY_8_CYCLES                7\r
+\r
+#define PL310_LATENCIES(Write,Read,Setup)      (((Write) << 8) | ((Read) << 4) | (Setup))\r
+#define PL310_TAG_LATENCIES(Write,Read,Setup)  PL310_LATENCIES(Write,Read,Setup)\r
+#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
+\r
+VOID\r
+L2x0CacheInit (\r
+  IN  UINTN   L2x0Base,\r
+  IN  UINT32  L2x0TagLatencies,\r
+  IN  UINT32  L2x0DataLatencies,\r
+  IN  UINT32  L2x0AuxValue,\r
+  IN  UINT32  L2x0AuxMask,\r
+  IN  BOOLEAN CacheEnabled\r
+  );\r
+\r
+#endif /* L2CACHELIB_H_ */\r