ArmPkg: Tidy GIC code before changes.

[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 4364f3ffef464596f64cf59881d703cf54cf0ddd..a4ede82bc6c07733f880a12fff54001590a0518a 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -17,9 +17,7 @@
 \r
 #include <Library/ArmGicArchLib.h>\r
 \r
-//\r
 // GIC Distributor\r
-//\r
 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register\r
 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
@@ -51,9 +49,7 @@
 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)\r
 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)\r
 \r
-//\r
 // GIC Redistributor\r
-//\r
 \r
 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB\r
 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
@@ -65,9 +61,7 @@
 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
 \r
-//\r
 // GIC Cpu interface\r
-//\r
 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register\r
 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register\r
@@ -104,9 +98,7 @@ ArmGicGetInterfaceIdentification (
   IN  INTN          GicInterruptInterfaceBase\r
   );\r
 \r
-//\r
 // GIC Secure interfaces\r
-//\r
 VOID\r
 EFIAPI\r
 ArmGicSetupNonSecure (\r
@@ -170,7 +162,8 @@ ArmGicSendSgiTo (
  * in the GICv3 the register value is only the InterruptId.\r
  *\r
  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface\r
- * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register\r
+ * @param InterruptId                 InterruptId read from the Interrupt\r
+ *                                    Acknowledge Register\r
  *\r
  * @retval value returned by the Interrupt Acknowledge Register\r
  *\r
@@ -220,12 +213,12 @@ ArmGicIsInterruptEnabled (
   IN UINTN                  Source\r
   );\r
 \r
-//\r
 // GIC revision 2 specific declarations\r
-//\r
 \r
-// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
-#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
+// Interrupts from 1020 to 1023 are considered as special interrupts\r
+// (eg: spurious interrupts)\r
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
+          (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
 \r
 VOID\r
 EFIAPI\r
@@ -260,9 +253,7 @@ ArmGicV2EndOfInterrupt (
   IN UINTN                  Source\r
   );\r
 \r
-//\r
 // GIC revision 3 specific declarations\r
-//\r
 \r
 #define ICC_SRE_EL2_SRE         (1 << 0)\r
 \r