ArmPkg/ArmGic: Added GICv3 specific definitions

[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index d00159b356280f42f34f7232179e5b2e3fe8a258..6cd93a1f54f64b7990546ee9a0fa3a12cd9812b3 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -30,7 +30,7 @@ typedef enum {
 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
@@ -38,10 +38,10 @@ typedef enum {
 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+// Each reg base below repeats for Number of interrupts / 4\r
 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+// Each reg base below repeats for Number of interrupts\r
 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
 \r
@@ -50,6 +50,23 @@ typedef enum {
 // just one of these\r
 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
 \r
+// GICv3 specific registers\r
+#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
+\r
+//\r
+// GIC Redistributor\r
+//\r
+\r
+#define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+\r
+// GIC Redistributor Control frame\r
+#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register\r
+\r
+// GIC SGI & PPI Redistributor frame\r
+#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
+\r
 //\r
 // GIC Cpu interface\r
 //\r