ArmPkg/ArmGic: Added GICv3 specific definitions

ARM GICv3 specification introduces some new components and registers.
This patch adds their definitions.

The most important GICv3 component is the GIC Redistributor. It supports
LPIs (Locality-specific peripheral Interrupt), 8+ CPU configuration.
Some GIC distributor registers have moved to the GIC redistributor.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Tested-by: Ard Biesheuvel <ard@linaro.org>
Reviewed-by: Ard Biesheuvel <ard@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16872 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index d7a4826d931a4885638f04f9d3b13564b96e6012..75960ed8df8dd5958856a0289c5c7cf437e70ed1 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -2,7 +2,7 @@
 # ARM processor package.\r
 #\r
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
 #\r
 #    This program and the accompanying materials\r
 #    are licensed and made available under the terms and conditions of the BSD License\r
@@ -240,5 +240,7 @@
   # ARM Generic Interrupt Controller\r
   #\r
   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+  # Base address for the GIC Redistributor region that contains the boot CPU\r
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
index 2d46706a764b9aac3730abe8e86da420720cd3f1..92f3b1d31282ad80cde0ed484da5ead3de9513bd 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -52,6 +52,7 @@
 \r
 [Pcd.common]\r
   gArmTokenSpaceGuid.PcdGicDistributorBase\r
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
 \r
 [Depex]\r

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index f756d308038617cbf659137f942b8abcafef806d..51212811e31d57f4954b4ee08579bf2f38233eee 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -20,6 +20,7 @@
 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;\r
 \r
 STATIC UINTN mGicDistributorBase;\r
+STATIC UINTN mGicRedistributorsBase;\r
 \r
 /**\r
   Enable interrupt source Source.\r
@@ -243,8 +244,9 @@ GicV3DxeInitialize (
   // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
 \r
-  mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);\r
-  mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
+  mGicDistributorBase    = PcdGet32 (PcdGicDistributorBase);\r
+  mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);\r
+  mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
 \r
   for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);\r

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index d00159b356280f42f34f7232179e5b2e3fe8a258..6cd93a1f54f64b7990546ee9a0fa3a12cd9812b3 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file\r
 *\r
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
 *\r
 *  This program and the accompanying materials\r
 *  are licensed and made available under the terms and conditions of the BSD License\r
@@ -30,7 +30,7 @@ typedef enum {
 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
@@ -38,10 +38,10 @@ typedef enum {
 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+// Each reg base below repeats for Number of interrupts / 4\r
 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
 \r
-// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+// Each reg base below repeats for Number of interrupts\r
 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
 \r
@@ -50,6 +50,23 @@ typedef enum {
 // just one of these\r
 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
 \r
+// GICv3 specific registers\r
+#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
+\r
+//\r
+// GIC Redistributor\r
+//\r
+\r
+#define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+\r
+// GIC Redistributor Control frame\r
+#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register\r
+\r
+// GIC SGI & PPI Redistributor frame\r
+#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
+\r
 //\r
 // GIC Cpu interface\r
 //\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc
index 7cc4e27271f85101aa5d123c1cc6d83a49704487..3ae6b327c1490cf4c8b6aeb16370919a373e7939 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc
@@ -1,5 +1,5 @@
 #\r
-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
+#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
 #\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
@@ -157,6 +157,7 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
 !else\r
   gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000\r
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000\r
 !endif\r
 \r