3 * Copyright (c) 2011-2015, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "ArmGicDxe.h"
16 #include "GicV3/ArmGicV3Lib.h"
18 #define ARM_GIC_DEFAULT_PRIORITY 0x80
20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol
;
22 STATIC UINTN mGicDistributorBase
;
23 STATIC UINTN mGicRedistributorsBase
;
26 Enable interrupt source Source.
28 @param This Instance pointer for this protocol
29 @param Source Hardware source of the interrupt
31 @retval EFI_SUCCESS Source interrupt enabled.
32 @retval EFI_DEVICE_ERROR Hardware could not be programmed.
37 GicV3EnableInterruptSource (
38 IN EFI_HARDWARE_INTERRUPT_PROTOCOL
*This
,
39 IN HARDWARE_INTERRUPT_SOURCE Source
42 if (Source
> mGicNumInterrupts
) {
44 return EFI_UNSUPPORTED
;
47 ArmGicEnableInterrupt (mGicDistributorBase
, Source
);
53 Disable interrupt source Source.
55 @param This Instance pointer for this protocol
56 @param Source Hardware source of the interrupt
58 @retval EFI_SUCCESS Source interrupt disabled.
59 @retval EFI_DEVICE_ERROR Hardware could not be programmed.
64 GicV3DisableInterruptSource (
65 IN EFI_HARDWARE_INTERRUPT_PROTOCOL
*This
,
66 IN HARDWARE_INTERRUPT_SOURCE Source
69 if (Source
> mGicNumInterrupts
) {
71 return EFI_UNSUPPORTED
;
74 ArmGicDisableInterrupt (mGicDistributorBase
, Source
);
80 Return current state of interrupt source Source.
82 @param This Instance pointer for this protocol
83 @param Source Hardware source of the interrupt
84 @param InterruptState TRUE: source enabled, FALSE: source disabled.
86 @retval EFI_SUCCESS InterruptState is valid
87 @retval EFI_DEVICE_ERROR InterruptState is not valid
92 GicV3GetInterruptSourceState (
93 IN EFI_HARDWARE_INTERRUPT_PROTOCOL
*This
,
94 IN HARDWARE_INTERRUPT_SOURCE Source
,
95 IN BOOLEAN
*InterruptState
98 if (Source
> mGicNumInterrupts
) {
100 return EFI_UNSUPPORTED
;
103 *InterruptState
= ArmGicIsInterruptEnabled (mGicDistributorBase
, Source
);
109 Signal to the hardware that the End Of Interrupt state
112 @param This Instance pointer for this protocol
113 @param Source Hardware source of the interrupt
115 @retval EFI_SUCCESS Source interrupt EOI'ed.
116 @retval EFI_DEVICE_ERROR Hardware could not be programmed.
121 GicV3EndOfInterrupt (
122 IN EFI_HARDWARE_INTERRUPT_PROTOCOL
*This
,
123 IN HARDWARE_INTERRUPT_SOURCE Source
126 if (Source
> mGicNumInterrupts
) {
128 return EFI_UNSUPPORTED
;
131 ArmGicV3EndOfInterrupt (Source
);
136 EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
138 @param InterruptType Defines the type of interrupt or exception that
139 occurred on the processor.This parameter is processor architecture specific.
140 @param SystemContext A pointer to the processor context when
141 the interrupt occurred on the processor.
148 GicV3IrqInterruptHandler (
149 IN EFI_EXCEPTION_TYPE InterruptType
,
150 IN EFI_SYSTEM_CONTEXT SystemContext
154 HARDWARE_INTERRUPT_HANDLER InterruptHandler
;
156 GicInterrupt
= ArmGicV3AcknowledgeInterrupt ();
158 // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
159 // number of interrupt (ie: Spurious interrupt).
160 if ((GicInterrupt
& ARM_GIC_ICCIAR_ACKINTID
) >= mGicNumInterrupts
) {
161 // The special interrupt do not need to be acknowledge
165 InterruptHandler
= gRegisteredInterruptHandlers
[GicInterrupt
];
166 if (InterruptHandler
!= NULL
) {
167 // Call the registered interrupt handler.
168 InterruptHandler (GicInterrupt
, SystemContext
);
170 DEBUG ((EFI_D_ERROR
, "Spurious GIC interrupt: 0x%x\n", GicInterrupt
));
173 GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol
, GicInterrupt
);
177 // The protocol instance produced by this driver
179 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol
= {
180 RegisterInterruptSource
,
181 GicV3EnableInterruptSource
,
182 GicV3DisableInterruptSource
,
183 GicV3GetInterruptSourceState
,
188 Shutdown our hardware
190 DXE Core will disable interrupts and turn off the timer and disable interrupts
191 after all the event handlers have run.
193 @param[in] Event The Event that is being processed
194 @param[in] Context Event Context
198 GicV3ExitBootServicesEvent (
205 // Acknowledge all pending interrupts
206 for (Index
= 0; Index
< mGicNumInterrupts
; Index
++) {
207 GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol
, Index
);
210 for (Index
= 0; Index
< mGicNumInterrupts
; Index
++) {
211 GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol
, Index
);
214 // Disable Gic Interface
215 ArmGicV3DisableInterruptInterface ();
217 // Disable Gic Distributor
218 ArmGicDisableDistributor (mGicDistributorBase
);
222 Initialize the state information for the CPU Architectural Protocol
224 @param ImageHandle of the loaded driver
225 @param SystemTable Pointer to the System Table
227 @retval EFI_SUCCESS Protocol registered
228 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
229 @retval EFI_DEVICE_ERROR Hardware problems
234 IN EFI_HANDLE ImageHandle
,
235 IN EFI_SYSTEM_TABLE
*SystemTable
244 // Make sure the Interrupt Controller Protocol is not already installed in the system.
245 ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL
, &gHardwareInterruptProtocolGuid
);
247 mGicDistributorBase
= PcdGet32 (PcdGicDistributorBase
);
248 mGicRedistributorsBase
= PcdGet32 (PcdGicRedistributorsBase
);
249 mGicNumInterrupts
= ArmGicGetMaxNumInterrupts (mGicDistributorBase
);
251 for (Index
= 0; Index
< mGicNumInterrupts
; Index
++) {
252 GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol
, Index
);
255 RegOffset
= Index
/ 4;
256 RegShift
= (Index
% 4) * 8;
258 mGicDistributorBase
+ ARM_GIC_ICDIPR
+ (4 * RegOffset
),
260 ARM_GIC_DEFAULT_PRIORITY
<< RegShift
265 // Targets the interrupts to the Primary Cpu
268 // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
269 // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
270 // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
271 // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
273 // Read the first Interrupt Processor Targets Register (that corresponds to the 4
275 CpuTarget
= MmioRead32 (mGicDistributorBase
+ ARM_GIC_ICDIPTR
);
277 // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
278 // is 0 when we run on a uniprocessor platform.
279 if (CpuTarget
!= 0) {
280 // The 8 first Interrupt Processor Targets Registers are read-only
281 for (Index
= 8; Index
< (mGicNumInterrupts
/ 4); Index
++) {
282 MmioWrite32 (mGicDistributorBase
+ ARM_GIC_ICDIPTR
+ (Index
* 4), CpuTarget
);
286 // Set binary point reg to 0x7 (no preemption)
287 ArmGicV3SetBinaryPointer (0x7);
289 // Set priority mask reg to 0xff to allow all priorities through
290 ArmGicV3SetPriorityMask (0xff);
292 // Enable gic cpu interface
293 ArmGicV3EnableInterruptInterface ();
295 // Enable gic distributor
296 ArmGicEnableDistributor (mGicDistributorBase
);
298 Status
= InstallAndRegisterInterruptService (
299 &gHardwareInterruptV3Protocol
, GicV3IrqInterruptHandler
, GicV3ExitBootServicesEvent
);