/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
-#ifndef __PL390GIC_H\r
-#define __PL390GIC_H\r
+#ifndef __ARMGIC_H\r
+#define __ARMGIC_H\r
\r
//\r
// GIC definitions\r
//\r
+typedef enum {\r
+ ARM_GIC_ARCH_REVISION_2,\r
+ ARM_GIC_ARCH_REVISION_3\r
+} ARM_GIC_ARCH_REVISION;\r
\r
//\r
// GIC Distributor\r
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+// Each reg base below repeats for Number of interrupts / 4\r
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
\r
-// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+// Each reg base below repeats for Number of interrupts\r
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
\r
+// GICv3 specific registers\r
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
+\r
+//\r
+// GIC Redistributor\r
+//\r
+\r
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+\r
+// GIC Redistributor Control frame\r
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
+\r
+// GIC SGI & PPI Redistributor frame\r
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
+\r
//\r
// GIC Cpu interface\r
//\r
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
-#define ARM_GIC_ICCIDR 0xFC // Identification Register\r
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
\r
+// Bit Mask for GICC_IIDR\r
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
+\r
+// Bit Mask for\r
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
+\r
+ARM_GIC_ARCH_REVISION\r
+EFIAPI\r
+ArmGicGetSupportedArchRevision (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicGetInterfaceIdentification (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
\r
//\r
// GIC Secure interfaces\r
IN INTN GicInterruptInterfaceBase\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
IN INTN GicDistributorBase\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicDisableDistributor (\r
+ IN INTN GicDistributorBase\r
+ );\r
+\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
IN INTN SgiId\r
);\r
\r
-UINT32\r
+/*\r
+ * Acknowledge and return the value of the Interrupt Acknowledge Register\r
+ *\r
+ * InterruptId is returned separately from the register value because in\r
+ * the GICv2 the register value contains the CpuId and InterruptId while\r
+ * in the GICv3 the register value is only the InterruptId.\r
+ *\r
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
+ * @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
+ *\r
+ * @retval value returned by the Interrupt Acknowledge Register\r
+ *\r
+ */\r
+UINTN\r
EFIAPI\r
-ArmGicAcknowledgeSgiFrom (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId\r
+ArmGicAcknowledgeInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *InterruptId\r
);\r
\r
-UINT32\r
+VOID\r
EFIAPI\r
-ArmGicAcknowledgeSgi2From (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId,\r
- IN INTN SgiId\r
+ArmGicEndOfInterrupt (\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ IN UINTN Source\r
);\r
\r
UINTN\r
IN INTN PriorityMask\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterrupt (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterrupt (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGicIsInterruptEnabled (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN Source\r
+ );\r
+\r
#endif\r
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