ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 8174845c6f2ddec060412713e6777b895d40b0b6..85fa1f600ba9e40fa09b74b75085ef7a5e7655ce 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-  Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -18,36 +18,14 @@
 \r
 #include <Uefi/UefiBaseType.h>\r
 \r
-#ifdef ARM_CPU_ARMv6\r
-#include <Chipset/ARM1176JZ-S.h>\r
+#ifdef MDE_CPU_ARM\r
+  #include <Chipset/ArmV7.h>\r
+#elif defined(MDE_CPU_AARCH64)\r
+  #include <Chipset/AArch64.h>\r
 #else\r
-#include <Chipset/ArmV7.h>\r
+ #error "Unknown chipset."\r
 #endif\r
 \r
-typedef enum {\r
-  ARM_CACHE_TYPE_WRITE_BACK,\r
-  ARM_CACHE_TYPE_UNKNOWN\r
-} ARM_CACHE_TYPE;\r
-\r
-typedef enum {\r
-  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
-  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
-  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
-} ARM_CACHE_ARCHITECTURE;\r
-\r
-typedef struct {\r
-  ARM_CACHE_TYPE          Type;\r
-  ARM_CACHE_ARCHITECTURE  Architecture;\r
-  BOOLEAN                 DataCachePresent;\r
-  UINTN                   DataCacheSize;\r
-  UINTN                   DataCacheAssociativity;\r
-  UINTN                   DataCacheLineLength;\r
-  BOOLEAN                 InstructionCachePresent;\r
-  UINTN                   InstructionCacheSize;\r
-  UINTN                   InstructionCacheAssociativity;\r
-  UINTN                   InstructionCacheLineLength;\r
-} ARM_CACHE_INFO;\r
-\r
 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
  *\r
@@ -70,7 +48,7 @@ typedef enum {
 typedef struct {\r
   EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
   EFI_VIRTUAL_ADDRESS           VirtualBase;\r
-  UINTN                         Length;\r
+  UINT64                        Length;\r
   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
 } ARM_MEMORY_REGION_DESCRIPTOR;\r
 \r
@@ -112,91 +90,57 @@ typedef enum {
 //\r
 // ARM MP Core IDs\r
 //\r
-#define ARM_CORE_MASK         0xFF\r
-#define ARM_CLUSTER_MASK      (0xFF << 8)\r
+#define ARM_CORE_AFF0         0xFF\r
+#define ARM_CORE_AFF1         (0xFF << 8)\r
+#define ARM_CORE_AFF2         (0xFF << 16)\r
+#define ARM_CORE_AFF3         (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK         ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
-// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
-//   Position = (ClusterId * 4) + CoreId\r
-#define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
-  VOID\r
-  );\r
-\r
-ARM_CACHE_ARCHITECTURE\r
+UINTN\r
 EFIAPI\r
-ArmCacheArchitecture (\r
+ArmDataCacheLineLength (\r
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmCacheInformation (\r
-  OUT ARM_CACHE_INFO  *CacheInfo\r
-  );\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
-  VOID\r
-  );\r
-  \r
 UINTN\r
 EFIAPI\r
-ArmDataCacheSize (\r
+ArmInstructionCacheLineLength (\r
   VOID\r
   );\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
-ArmDataCacheAssociativity (\r
+ArmCacheWritebackGranule (\r
   VOID\r
   );\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
-ArmDataCacheLineLength (\r
-  VOID\r
-  );\r
-  \r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
+ArmIsArchTimerImplemented (\r
   VOID\r
   );\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
-ArmInstructionCacheSize (\r
+ArmReadIdPfr0 (\r
   VOID\r
   );\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
-ArmInstructionCacheAssociativity (\r
+ArmReadIdPfr1 (\r
   VOID\r
   );\r
-  \r
+\r
 UINTN\r
 EFIAPI\r
-ArmInstructionCacheLineLength (\r
-  VOID\r
-  );\r
-  \r
-UINT32\r
-EFIAPI\r
-Cp15IdCode (\r
-  VOID\r
-  );\r
-  \r
-UINT32\r
-EFIAPI\r
-Cp15CacheInfo (\r
+ArmCacheInfo (\r
   VOID\r
   );\r
 \r
@@ -225,12 +169,6 @@ ArmCleanDataCache (
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheToPoU (\r
-  VOID\r
-  );\r
-\r
 VOID\r
 EFIAPI\r
 ArmInvalidateInstructionCache (\r
@@ -245,16 +183,40 @@ ArmInvalidateDataCacheEntryByMVA (
 \r
 VOID\r
 EFIAPI\r
-ArmCleanDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA(\r
   IN  UINTN   Address\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA(\r
+IN  UINTN   Address\r
+);\r
+\r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
   IN  UINTN   Address\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+  IN  UINTN  SetWayFormat\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+  IN  UINTN  SetWayFormat\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+  IN  UINTN   SetWayFormat\r
+  );\r
+\r
 VOID\r
 EFIAPI\r
 ArmEnableDataCache (\r
@@ -278,7 +240,7 @@ EFIAPI
 ArmDisableInstructionCache (\r
   VOID\r
   );\r
-  \r
+\r
 VOID\r
 EFIAPI\r
 ArmEnableMmu (\r
@@ -293,13 +255,13 @@ ArmDisableMmu (
 \r
 VOID\r
 EFIAPI\r
-ArmDisableCachesAndMmu (\r
+ArmEnableCachesAndMmu (\r
   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
+ArmDisableCachesAndMmu (\r
   VOID\r
   );\r
 \r
@@ -321,9 +283,15 @@ ArmGetInterruptState (
   VOID\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+  VOID\r
+  );\r
+\r
 UINTN\r
 EFIAPI\r
-ArmDisableIrq (\r
+ArmDisableAsynchronousAbort (\r
   VOID\r
   );\r
 \r
@@ -333,6 +301,12 @@ ArmEnableIrq (
   VOID\r
   );\r
 \r
+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+  VOID\r
+  );\r
+\r
 VOID\r
 EFIAPI\r
 ArmEnableFiq (\r
@@ -344,26 +318,29 @@ EFIAPI
 ArmDisableFiq (\r
   VOID\r
   );\r
-  \r
+\r
 BOOLEAN\r
 EFIAPI\r
 ArmGetFiqState (\r
   VOID\r
   );\r
 \r
+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r
 VOID\r
 EFIAPI\r
 ArmInvalidateTlb (\r
   VOID\r
   );\r
-  \r
+\r
 VOID\r
 EFIAPI\r
 ArmUpdateTranslationTableEntry (\r
   IN  VOID     *TranslationTableEntry,\r
   IN  VOID     *Mva\r
   );\r
-  \r
+\r
 VOID\r
 EFIAPI\r
 ArmSetDomainAccessControl (\r
@@ -389,25 +366,13 @@ ArmConfigureMmu (
   OUT VOID                         **TranslationTableBase OPTIONAL,\r
   OUT UINTN                         *TranslationTableSize  OPTIONAL\r
   );\r
-  \r
+\r
 BOOLEAN\r
 EFIAPI\r
 ArmMmuEnabled (\r
   VOID\r
   );\r
-  \r
-VOID\r
-EFIAPI\r
-ArmSwitchProcessorMode (\r
-  IN ARM_PROCESSOR_MODE Mode\r
-  );\r
 \r
-ARM_PROCESSOR_MODE\r
-EFIAPI\r
-ArmProcessorMode (\r
-  VOID\r
-  );\r
-  \r
 VOID\r
 EFIAPI\r
 ArmEnableBranchPrediction (\r
@@ -437,13 +402,13 @@ EFIAPI
 ArmDataMemoryBarrier (\r
   VOID\r
   );\r
-  \r
+\r
 VOID\r
 EFIAPI\r
-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r
   VOID\r
   );\r
-  \r
+\r
 VOID\r
 EFIAPI\r
 ArmInstructionSynchronizationBarrier (\r
@@ -453,10 +418,10 @@ ArmInstructionSynchronizationBarrier (
 VOID\r
 EFIAPI\r
 ArmWriteVBar (\r
-  IN  UINT32   VectorBase\r
+  IN  UINTN   VectorBase\r
   );\r
 \r
-UINT32\r
+UINTN\r
 EFIAPI\r
 ArmReadVBar (\r
   VOID\r
@@ -501,6 +466,7 @@ ArmCallWFE (
 VOID\r
 EFIAPI\r
 ArmCallWFI (\r
+\r
   VOID\r
   );\r
 \r
@@ -510,6 +476,12 @@ ArmReadMpidr (
   VOID\r
   );\r
 \r
+UINTN\r
+EFIAPI\r
+ArmReadMidr (\r
+  VOID\r
+  );\r
+\r
 UINT32\r
 EFIAPI\r
 ArmReadCpacr (\r
@@ -528,28 +500,28 @@ ArmEnableVFP (
   VOID\r
   );\r
 \r
-UINT32\r
-EFIAPI\r
-ArmReadNsacr (\r
-  VOID\r
-  );\r
+/**\r
+  Get the Secure Configuration Register value\r
 \r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
-  IN  UINT32   SetWayFormat\r
-  );\r
+  @return   Value read from the Secure Configuration Register\r
 \r
+**/\r
 UINT32\r
 EFIAPI\r
 ArmReadScr (\r
   VOID\r
   );\r
 \r
+/**\r
+  Set the Secure Configuration Register\r
+\r
+  @param Value   Value to write to the Secure Configuration Register\r
+\r
+**/\r
 VOID\r
 EFIAPI\r
 ArmWriteScr (\r
-  IN  UINT32   SetWayFormat\r
+  IN  UINT32   Value\r
   );\r
 \r
 UINT32\r
@@ -582,4 +554,57 @@ ArmWriteHVBar (
   IN  UINTN   HypModeVectorBase\r
   );\r
 \r
+\r
+//\r
+// Helper functions for accessing CPU ACTLR\r
+//\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCpuActlr (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpuActlr (\r
+  IN  UINTN Val\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+  IN  UINTN    Bits\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+  IN  UINTN    Bits\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmSetMemoryRegionNoExec (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmClearMemoryRegionNoExec (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmSetMemoryRegionReadOnly (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmClearMemoryRegionReadOnly (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
 #endif // __ARM_LIB__\r