ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index b4768841bd9daf107f8365631efdf47cfd030cec..85fa1f600ba9e40fa09b74b75085ef7a5e7655ce 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -26,30 +26,6 @@
  #error "Unknown chipset."\r
 #endif\r
 \r
-typedef enum {\r
-  ARM_CACHE_TYPE_WRITE_BACK,\r
-  ARM_CACHE_TYPE_UNKNOWN\r
-} ARM_CACHE_TYPE;\r
-\r
-typedef enum {\r
-  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
-  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
-  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
-} ARM_CACHE_ARCHITECTURE;\r
-\r
-typedef struct {\r
-  ARM_CACHE_TYPE          Type;\r
-  ARM_CACHE_ARCHITECTURE  Architecture;\r
-  BOOLEAN                 DataCachePresent;\r
-  UINTN                   DataCacheSize;\r
-  UINTN                   DataCacheAssociativity;\r
-  UINTN                   DataCacheLineLength;\r
-  BOOLEAN                 InstructionCachePresent;\r
-  UINTN                   InstructionCacheSize;\r
-  UINTN                   InstructionCacheAssociativity;\r
-  UINTN                   InstructionCacheLineLength;\r
-} ARM_CACHE_INFO;\r
-\r
 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
  *\r
@@ -126,69 +102,21 @@ typedef enum {
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
-  VOID\r
-  );\r
-\r
-ARM_CACHE_ARCHITECTURE\r
-EFIAPI\r
-ArmCacheArchitecture (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCacheInformation (\r
-  OUT ARM_CACHE_INFO  *CacheInfo\r
-  );\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheSize (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheAssociativity (\r
-  VOID\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
 ArmDataCacheLineLength (\r
   VOID\r
   );\r
 \r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
-  VOID\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
-ArmInstructionCacheSize (\r
+ArmInstructionCacheLineLength (\r
   VOID\r
   );\r
 \r
 UINTN\r
 EFIAPI\r
-ArmInstructionCacheAssociativity (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
+ArmCacheWritebackGranule (\r
   VOID\r
   );\r
 \r
@@ -241,12 +169,6 @@ ArmCleanDataCache (
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheToPoU (\r
-  VOID\r
-  );\r
-\r
 VOID\r
 EFIAPI\r
 ArmInvalidateInstructionCache (\r
@@ -261,10 +183,16 @@ ArmInvalidateDataCacheEntryByMVA (
 \r
 VOID\r
 EFIAPI\r
-ArmCleanDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA(\r
   IN  UINTN   Address\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA(\r
+IN  UINTN   Address\r
+);\r
+\r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
@@ -469,12 +397,6 @@ ArmSetHighVectors (
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmDrainWriteBuffer (\r
-  VOID\r
-  );\r
-\r
 VOID\r
 EFIAPI\r
 ArmDataMemoryBarrier (\r
@@ -483,7 +405,7 @@ ArmDataMemoryBarrier (
 \r
 VOID\r
 EFIAPI\r
-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r
   VOID\r
   );\r
 \r