ArmPkg/ArmLib: add support for reading the max physical address space size

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 1726984f5baf142672fb7b73904293f62f8dbf0f..9a804c15fdb6f168528d7383db7688fccc01dc7d 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r

-  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r

 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r


@@ -19,40 +19,16 @@
 #include <Uefi/UefiBaseType.h>\r
 \r
 #ifdef MDE_CPU_ARM\r
 #include <Uefi/UefiBaseType.h>\r
 \r
 #ifdef MDE_CPU_ARM\r

-  #ifdef ARM_CPU_ARMv6\r
-    #include <Chipset/ARM1176JZ-S.h>\r
-  #else\r
-    #include <Chipset/ArmV7.h>\r
-  #endif\r
+  #include <Chipset/ArmV7.h>\r

 #elif defined(MDE_CPU_AARCH64)\r
   #include <Chipset/AArch64.h>\r
 #else\r
  #error "Unknown chipset."\r
 #endif\r
 \r
 #elif defined(MDE_CPU_AARCH64)\r
   #include <Chipset/AArch64.h>\r
 #else\r
  #error "Unknown chipset."\r
 #endif\r
 \r

-typedef enum {\r
-  ARM_CACHE_TYPE_WRITE_BACK,\r
-  ARM_CACHE_TYPE_UNKNOWN\r
-} ARM_CACHE_TYPE;\r
-\r
-typedef enum {\r
-  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
-  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
-  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
-} ARM_CACHE_ARCHITECTURE;\r
-\r
-typedef struct {\r
-  ARM_CACHE_TYPE          Type;\r
-  ARM_CACHE_ARCHITECTURE  Architecture;\r
-  BOOLEAN                 DataCachePresent;\r
-  UINTN                   DataCacheSize;\r
-  UINTN                   DataCacheAssociativity;\r
-  UINTN                   DataCacheLineLength;\r
-  BOOLEAN                 InstructionCachePresent;\r
-  UINTN                   InstructionCacheSize;\r
-  UINTN                   InstructionCacheAssociativity;\r
-  UINTN                   InstructionCacheLineLength;\r
-} ARM_CACHE_INFO;\r
+#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
+                                     EFI_MEMORY_UCE)\r

 \r
 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 \r
 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r


@@ -65,6 +41,14 @@ typedef enum {
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r

+\r
+  // On some platforms, memory mapped flash region is designed as not supporting\r
+  // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
+  // need.\r
+  // Do NOT use below two attributes if you are not sure.\r
+  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
+  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
+\r

   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r


@@ -118,79 +102,33 @@ typedef enum {
 //\r
 // ARM MP Core IDs\r
 //\r
 //\r
 // ARM MP Core IDs\r
 //\r

-#define ARM_CORE_MASK         0xFF\r
-#define ARM_CLUSTER_MASK      (0xFF << 8)\r
+#define ARM_CORE_AFF0         0xFF\r
+#define ARM_CORE_AFF1         (0xFF << 8)\r
+#define ARM_CORE_AFF2         (0xFF << 16)\r
+#define ARM_CORE_AFF3         (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK         ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r

 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r

-// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
-//   Position = (ClusterId * 4) + CoreId\r
-#define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r

 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r

-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
-  VOID\r
-  );\r
-\r
-ARM_CACHE_ARCHITECTURE\r
-EFIAPI\r
-ArmCacheArchitecture (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCacheInformation (\r
-  OUT ARM_CACHE_INFO  *CacheInfo\r
-  );\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
-  VOID\r
-  );\r
-  \r
-UINTN\r
-EFIAPI\r
-ArmDataCacheSize (\r
-  VOID\r
-  );\r
-  \r
-UINTN\r
-EFIAPI\r
-ArmDataCacheAssociativity (\r
-  VOID\r
-  );\r
-  \r

 UINTN\r
 EFIAPI\r
 ArmDataCacheLineLength (\r
   VOID\r
   );\r
 UINTN\r
 EFIAPI\r
 ArmDataCacheLineLength (\r
   VOID\r
   );\r

-  \r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
-  VOID\r
-  );\r
-  \r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheSize (\r
-  VOID\r
-  );\r
-  \r
+\r

 UINTN\r
 EFIAPI\r
 UINTN\r
 EFIAPI\r

-ArmInstructionCacheAssociativity (\r
+ArmInstructionCacheLineLength (\r

   VOID\r
   );\r
   VOID\r
   );\r

-  \r
+\r

 UINTN\r
 EFIAPI\r
 UINTN\r
 EFIAPI\r

-ArmInstructionCacheLineLength (\r
+ArmCacheWritebackGranule (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -212,15 +150,9 @@ ArmReadIdPfr1 (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

-UINT32\r
-EFIAPI\r
-Cp15IdCode (\r
-  VOID\r
-  );\r
-  \r
-UINT32\r
+UINTN\r

 EFIAPI\r
 EFIAPI\r

-Cp15CacheInfo (\r
+ArmCacheInfo (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -251,34 +183,58 @@ ArmCleanDataCache (
 \r
 VOID\r
 EFIAPI\r
 \r
 VOID\r
 EFIAPI\r

-ArmCleanDataCacheToPoU (\r
+ArmInvalidateInstructionCache (\r

   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r
   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmInvalidateInstructionCache (\r
-  VOID\r
+ArmInvalidateDataCacheEntryByMVA (\r
+  IN  UINTN   Address\r

   );\r
 \r
 VOID\r
 EFIAPI\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmInvalidateDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA (\r

   IN  UINTN   Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
   IN  UINTN   Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmCleanDataCacheEntryByMVA (\r
+ArmInvalidateInstructionCacheEntryToPoUByMVA (\r

   IN  UINTN   Address\r
   );\r
 \r
   IN  UINTN   Address\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA (\r
+IN  UINTN   Address\r
+);\r
+\r

 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
   IN  UINTN   Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
   IN  UINTN   Address\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+  IN  UINTN  SetWayFormat\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+  IN  UINTN  SetWayFormat\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+  IN  UINTN   SetWayFormat\r
+  );\r
+\r

 VOID\r
 EFIAPI\r
 ArmEnableDataCache (\r
 VOID\r
 EFIAPI\r
 ArmEnableDataCache (\r


@@ -302,7 +258,7 @@ EFIAPI
 ArmDisableInstructionCache (\r
   VOID\r
   );\r
 ArmDisableInstructionCache (\r
   VOID\r
   );\r

-  \r
+\r

 VOID\r
 EFIAPI\r
 ArmEnableMmu (\r
 VOID\r
 EFIAPI\r
 ArmEnableMmu (\r


@@ -317,13 +273,13 @@ ArmDisableMmu (
 \r
 VOID\r
 EFIAPI\r
 \r
 VOID\r
 EFIAPI\r

-ArmDisableCachesAndMmu (\r
+ArmEnableCachesAndMmu (\r

   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r
   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmInvalidateInstructionAndDataTlb (\r
+ArmDisableCachesAndMmu (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -345,9 +301,15 @@ ArmGetInterruptState (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+  VOID\r
+  );\r
+\r

 UINTN\r
 EFIAPI\r
 UINTN\r
 EFIAPI\r

-ArmDisableIrq (\r
+ArmDisableAsynchronousAbort (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -357,6 +319,12 @@ ArmEnableIrq (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+  VOID\r
+  );\r
+\r

 VOID\r
 EFIAPI\r
 ArmEnableFiq (\r
 VOID\r
 EFIAPI\r
 ArmEnableFiq (\r


@@ -368,26 +336,29 @@ EFIAPI
 ArmDisableFiq (\r
   VOID\r
   );\r
 ArmDisableFiq (\r
   VOID\r
   );\r

-  \r
+\r

 BOOLEAN\r
 EFIAPI\r
 ArmGetFiqState (\r
   VOID\r
   );\r
 \r
 BOOLEAN\r
 EFIAPI\r
 ArmGetFiqState (\r
   VOID\r
   );\r
 \r

+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r

 VOID\r
 EFIAPI\r
 ArmInvalidateTlb (\r
   VOID\r
   );\r
 VOID\r
 EFIAPI\r
 ArmInvalidateTlb (\r
   VOID\r
   );\r

-  \r
+\r

 VOID\r
 EFIAPI\r
 ArmUpdateTranslationTableEntry (\r
   IN  VOID     *TranslationTableEntry,\r
   IN  VOID     *Mva\r
   );\r
 VOID\r
 EFIAPI\r
 ArmUpdateTranslationTableEntry (\r
   IN  VOID     *TranslationTableEntry,\r
   IN  VOID     *Mva\r
   );\r

-  \r
+\r

 VOID\r
 EFIAPI\r
 ArmSetDomainAccessControl (\r
 VOID\r
 EFIAPI\r
 ArmSetDomainAccessControl (\r


@@ -400,38 +371,24 @@ ArmSetTTBR0 (
   IN  VOID  *TranslationTableBase\r
   );\r
 \r
   IN  VOID  *TranslationTableBase\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmSetTTBCR (\r
+  IN  UINT32 Bits\r
+  );\r
+\r

 VOID *\r
 EFIAPI\r
 ArmGetTTBR0BaseAddress (\r
   VOID\r
   );\r
 \r
 VOID *\r
 EFIAPI\r
 ArmGetTTBR0BaseAddress (\r
   VOID\r
   );\r
 \r

-RETURN_STATUS\r
-EFIAPI\r
-ArmConfigureMmu (\r
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
-  OUT VOID                         **TranslationTableBase OPTIONAL,\r
-  OUT UINTN                         *TranslationTableSize  OPTIONAL\r
-  );\r
-  \r

 BOOLEAN\r
 EFIAPI\r
 ArmMmuEnabled (\r
   VOID\r
   );\r
 BOOLEAN\r
 EFIAPI\r
 ArmMmuEnabled (\r
   VOID\r
   );\r

-  \r
-VOID\r
-EFIAPI\r
-ArmSwitchProcessorMode (\r
-  IN ARM_PROCESSOR_MODE Mode\r
-  );\r

 \r
 \r

-ARM_PROCESSOR_MODE\r
-EFIAPI\r
-ArmProcessorMode (\r
-  VOID\r
-  );\r
-  \r

 VOID\r
 EFIAPI\r
 ArmEnableBranchPrediction (\r
 VOID\r
 EFIAPI\r
 ArmEnableBranchPrediction (\r


@@ -461,13 +418,13 @@ EFIAPI
 ArmDataMemoryBarrier (\r
   VOID\r
   );\r
 ArmDataMemoryBarrier (\r
   VOID\r
   );\r

-  \r
+\r

 VOID\r
 EFIAPI\r
 VOID\r
 EFIAPI\r

-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r

   VOID\r
   );\r
   VOID\r
   );\r

-  \r
+\r

 VOID\r
 EFIAPI\r
 ArmInstructionSynchronizationBarrier (\r
 VOID\r
 EFIAPI\r
 ArmInstructionSynchronizationBarrier (\r


@@ -559,16 +516,28 @@ ArmEnableVFP (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

+/**\r
+  Get the Secure Configuration Register value\r
+\r
+  @return   Value read from the Secure Configuration Register\r
+\r
+**/\r

 UINT32\r
 EFIAPI\r
 ArmReadScr (\r
   VOID\r
   );\r
 \r
 UINT32\r
 EFIAPI\r
 ArmReadScr (\r
   VOID\r
   );\r
 \r

+/**\r
+  Set the Secure Configuration Register\r
+\r
+  @param Value   Value to write to the Secure Configuration Register\r
+\r
+**/\r

 VOID\r
 EFIAPI\r
 ArmWriteScr (\r
 VOID\r
 EFIAPI\r
 ArmWriteScr (\r

-  IN  UINT32   SetWayFormat\r
+  IN  UINT32   Value\r

   );\r
 \r
 UINT32\r
   );\r
 \r
 UINT32\r


@@ -589,6 +558,12 @@ ArmReadSctlr (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmWriteSctlr (\r
+  IN  UINT32   Value\r
+  );\r
+\r

 UINTN\r
 EFIAPI\r
 ArmReadHVBar (\r
 UINTN\r
 EFIAPI\r
 ArmReadHVBar (\r


@@ -601,4 +576,167 @@ ArmWriteHVBar (
   IN  UINTN   HypModeVectorBase\r
   );\r
 \r
   IN  UINTN   HypModeVectorBase\r
   );\r
 \r

+\r
+//\r
+// Helper functions for accessing CPU ACTLR\r
+//\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCpuActlr (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpuActlr (\r
+  IN  UINTN Val\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+  IN  UINTN    Bits\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+  IN  UINTN    Bits\r
+  );\r
+\r
+//\r
+// Accessors for the architected generic timer registers\r
+//\r
+\r
+#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntFrq (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntFrq (\r
+  UINTN   FreqInHz\r
+  );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntPct (\r
+  VOID\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntkCtl (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntkCtl (\r
+  UINTN   Val\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpTval (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpTval (\r
+  UINTN   Val\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpCtl (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCtl (\r
+  UINTN   Val\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvTval (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvTval (\r
+  UINTN   Val\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvCtl (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCtl (\r
+  UINTN   Val\r
+  );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCt (\r
+  VOID\r
+  );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntpCval (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCval (\r
+  UINT64   Val\r
+  );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCval (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCval (\r
+  UINT64   Val\r
+  );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvOff (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvOff (\r
+  UINT64   Val\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGetPhysicalAddressBits (\r
+  VOID\r
+  );\r
+\r

 #endif // __ARM_LIB__\r
 #endif // __ARM_LIB__\r