Default exception handler\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINTN Index, Start, End;\r
CHAR8 *Str;\r
BOOLEAN First;\r
- \r
+\r
Str = mMregListStr;\r
*Str = '\0';\r
AsciiStrCat (Str, "{");\r
for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {\r
End = Index;\r
}\r
- \r
+\r
if (!First) {\r
AsciiStrCat (Str, ",");\r
} else {\r
First = FALSE;\r
}\r
- \r
+\r
if (Start == End) {\r
AsciiStrCat (Str, gReg[Start]);\r
AsciiStrCat (Str, ", ");\r
AsciiStrCat (Str, "ERROR");\r
}\r
AsciiStrCat (Str, "}");\r
- \r
+\r
// BugBug: Make caller pass in buffer it is cleaner\r
return mMregListStr;\r
}\r
\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtr Pointer to pointer of ARM instruction to disassemble. \r
+\r
+ @param OpCodePtr Pointer to pointer of ARM instruction to disassemble.\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
+ @param Size Size of Buf in bytes.\r
@param Extended TRUE dump hex for instruction too.\r
- \r
+\r
**/\r
VOID\r
DisassembleArmInstruction (\r
P = (OpCode & BIT24) == BIT24;\r
U = (OpCode & BIT23) == BIT23;\r
B = (OpCode & BIT22) == BIT22; // Also called S\r
- W = (OpCode & BIT21) == BIT21; \r
+ W = (OpCode & BIT21) == BIT21;\r
L = (OpCode & BIT20) == BIT20;\r
S = (OpCode & BIT6) == BIT6;\r
H = (OpCode & BIT5) == BIT5;\r
// LDREX, STREX\r
if ((OpCode & 0x0fe000f0) == 0x01800090) {\r
if (L) {\r
- // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>] \r
- AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); \r
+ // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]\r
+ AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);\r
} else {\r
// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]\r
- AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]); \r
- } \r
+ AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);\r
+ }\r
return;\r
}\r
- \r
+\r
// LDM/STM\r
if ((OpCode & 0x0e000000) == 0x08000000) {\r
if (L) {\r
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^\r
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^\r
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); \r
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
} else {\r
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>\r
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^\r
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B)); \r
- } \r
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));\r
+ }\r
return;\r
}\r
\r
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {\r
Index = AsciiSPrint (Buf, Size, "PLD");\r
} else {\r
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]); \r
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);\r
}\r
if (P) {\r
if (!I) {\r
} else {\r
Type = "ROR";\r
}\r
- \r
+\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));\r
}\r
} else { // !P\r
} else {\r
Type = "ROR";\r
}\r
- \r
+\r
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);\r
}\r
}\r
- return; \r
+ return;\r
}\r
- \r
+\r
if ((OpCode & 0x0e000000) == 0x00000000) {\r
// LDR/STR address mode 3\r
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>\r
Root = "STR%aD %a ";\r
}\r
}\r
- \r
- Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); \r
+\r
+ Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);\r
\r
S = (OpCode & BIT6) == BIT6;\r
H = (OpCode & BIT5) == BIT5;\r
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {\r
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}\r
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));\r
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0xfff000f0) == 0xe1200070) {\r
// A4.1.7 BKPT <immed_16>\r
AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);\r
return;\r
- } \r
- \r
+ }\r
+\r
if ((OpCode & 0xfff10020) == 0xf1000000) {\r
// A4.1.16 CPS<effect> <iflags> {, #<mode>}\r
if (((OpCode >> 6) & 0x7) == 0) {\r
}\r
}\r
return;\r
- } \r
- \r
+ }\r
+\r
if ((OpCode & 0x0f000000) == 0x0f000000) {\r
// A4.1.107 SWI{<cond>} <immed_24>\r
AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);\r
return;\r
- } \r
+ }\r
\r
if ((OpCode & 0x0fb00000) == 0x01000000) {\r
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR\r
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");\r
return;\r
- } \r
+ }\r
\r
\r
if ((OpCode & 0x0db00000) == 0x03200000) {\r
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);\r
}\r
return;\r
- } \r
+ }\r
\r
if ((OpCode & 0xff000010) == 0xfe000000) {\r
// A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>\r
AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);\r
return;\r
}\r
- \r
+\r
if ((OpCode & 0x0e000000) == 0x0c000000) {\r
// A4.1.19 LDC and A4.1.96 SDC\r
if ((OpCode & 0xf0000000) == 0xf0000000) {\r
} else {\r
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);\r
}\r
- \r
+\r
if (!P) {\r
- if (!W) { \r
+ if (!W) {\r
// A5.5.5.5 [<Rn>], <option>\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);\r
} else {\r
// A.5.5.4 [<Rn>], #+/-<offset_8>*4\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);\r
}\r
} else {\r
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!\r
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W)); \r
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));\r
}\r
- \r
+\r
}\r
- \r
+\r
if ((OpCode & 0x0f000010) == 0x0e000010) {\r
- // A4.1.32 MRC2, MCR2 \r
+ // A4.1.32 MRC2, MCR2\r
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);\r
- return; \r
+ return;\r
}\r
\r
if ((OpCode & 0x0ff00000) == 0x0c400000) {\r
- // A4.1.33 MRRC2, MCRR2 \r
+ // A4.1.33 MRRC2, MCRR2\r
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);\r
- return; \r
+ return;\r
}\r
\r
AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);\r
- \r
+\r
*OpCodePtr += 1;\r
return;\r
}\r
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