/** @file\r
Thumb Dissassembler. Still a work in progress.\r
\r
- Wrong output is a bug, so please fix it. \r
+ Wrong output is a bug, so please fix it.\r
Hex output means there is not yet an entry or a decode bug.\r
- gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit \r
- 16-bit stream of Thumb2 instruction. Then there are big case \r
+ gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit\r
+ 16-bit stream of Thumb2 instruction. Then there are big case\r
statements to print everything out. If you are adding instructions\r
try to reuse existing case entries if possible.\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
- \r
+\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
// Thumb address modes\r
#define LOAD_STORE_FORMAT1 1\r
#define LOAD_STORE_FORMAT1_H 101\r
-#define LOAD_STORE_FORMAT1_B 111 \r
+#define LOAD_STORE_FORMAT1_B 111\r
#define LOAD_STORE_FORMAT2 2\r
#define LOAD_STORE_FORMAT3 3\r
#define LOAD_STORE_FORMAT4 4\r
-#define LOAD_STORE_MULTIPLE_FORMAT1 5 \r
-#define PUSH_FORMAT 6 \r
-#define POP_FORMAT 106 \r
+#define LOAD_STORE_MULTIPLE_FORMAT1 5\r
+#define PUSH_FORMAT 6\r
+#define POP_FORMAT 106\r
#define IMMED_8 7\r
#define CONDITIONAL_BRANCH 8\r
#define UNCONDITIONAL_BRANCH 9\r
#define THUMB2_4REGS 230\r
#define ADD_IMM12_1REG 231\r
#define THUMB2_IMM16 232\r
-#define MRC_THUMB2 233 \r
-#define MRRC_THUMB2 234 \r
+#define MRC_THUMB2 233\r
+#define MRRC_THUMB2 234\r
#define THUMB2_MRS 235\r
#define THUMB2_MSR 236\r
\r
{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },\r
{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9\r
{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },\r
- { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP }, \r
+ { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },\r
{ "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },\r
\r
{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },\r
{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },\r
{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]\r
{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },\r
- \r
+\r
{ "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL\r
{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },\r
{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },\r
\r
THUMB_INSTRUCTIONS gOpThumb2[] = {\r
//Instruct OpCode OpCode Mask Addressig Mode\r
- \r
- { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW \r
+\r
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW\r
{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD\r
{ "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}\r
{ "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
{ "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>\r
{ "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>\r
{ "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>\r
- \r
+\r
{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
{ "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
\r
{ "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm> \r
+ { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>\r
{ "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm> \r
+ { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>\r
{ "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2\r
- { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm> \r
+ { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>\r
\r
{ "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>\r
{ "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>\r
{ "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>\r
{ "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>\r
{ "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>\r
- \r
+\r
{ "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}\r
{ "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}\r
\r
- { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label> \r
- { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label> \r
- { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label> \r
- { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
- { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label> \r
- \r
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>\r
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>\r
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>\r
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>\r
+\r
{ "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}\r
{ "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}\r
{ "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
- { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form? \r
- { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]} \r
- { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]} \r
- { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]} \r
+ { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?\r
+ { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}\r
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}\r
\r
{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>\r
- \r
- { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]] \r
- { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>] \r
- { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>] \r
- \r
- { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>] \r
-\r
- { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]} \r
+\r
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]\r
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]\r
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]\r
+\r
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]\r
+\r
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}\r
{ "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}\r
{ "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}\r
- \r
+\r
{ "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}\r
{ "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}\r
{ "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}\r
{ "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}\r
- { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]} \r
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}\r
\r
{ "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
\r
- { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]] \r
- { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>] \r
- { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>] \r
- \r
- { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>] \r
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]\r
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]\r
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]\r
+\r
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]\r
\r
{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>\r
{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>\r
UINTN Index, Start, End;\r
CHAR8 *Str;\r
BOOLEAN First;\r
- \r
+\r
Str = mThumbMregListStr;\r
*Str = '\0';\r
AsciiStrCat (Str, "{");\r
- \r
+\r
for (Index = 0, First = TRUE; Index <= 15; Index++) {\r
if ((RegBitMask & (1 << Index)) != 0) {\r
Start = End = Index;\r
for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {\r
End = Index;\r
}\r
- \r
+\r
if (!First) {\r
AsciiStrCat (Str, ",");\r
} else {\r
First = FALSE;\r
}\r
- \r
+\r
if (Start == End) {\r
AsciiStrCat (Str, gReg[Start]);\r
} else {\r
AsciiStrCat (Str, "ERROR");\r
}\r
AsciiStrCat (Str, "}");\r
- \r
+\r
// BugBug: Make caller pass in buffer it is cleaner\r
return mThumbMregListStr;\r
}\r
if (((Data & TopBit) == 0) || (TopBit == BIT31)) {\r
return Data;\r
}\r
- \r
+\r
do {\r
TopBit <<= 1;\r
- Data |= TopBit; \r
+ Data |= TopBit;\r
} while ((TopBit & BIT31) != BIT31);\r
\r
return Data;\r
}\r
\r
//\r
-// Some instructions specify the PC is always considered aligned \r
+// Some instructions specify the PC is always considered aligned\r
// The PC is after the instruction that is excuting. So you pass\r
// in the instruction address and you get back the aligned answer\r
//\r
}\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
+\r
+ @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
+ @param Size Size of Buf in bytes.\r
@param Extended TRUE dump hex for instruction too.\r
- \r
+\r
**/\r
VOID\r
DisassembleThumbInstruction (\r
UINT32 PC, Target, msbit, lsbit;\r
CHAR8 *Cond;\r
BOOLEAN S, J1, J2, P, U, W;\r
- UINT32 coproc, opc1, opc2, CRd, CRn, CRm; \r
+ UINT32 coproc, opc1, opc2, CRd, CRn, CRm;\r
UINT32 Mask;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
OpCode = **OpCodePtrPtr;\r
- \r
+\r
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.\r
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);\r
\r
\r
// Increment by the minimum instruction size, Thumb2 could be bigger\r
*OpCodePtrPtr += 1;\r
- \r
+\r
// Manage IT Block ItFlag TRUE means we are in an IT block\r
/*if (*ItBlock != 0) {\r
ItFlag = TRUE;\r
for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {\r
if (Extended) {\r
- Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);\r
} else {\r
- Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);\r
}\r
switch (gOpThumb[Index].AddressMode) {\r
case LOAD_STORE_FORMAT1:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);\r
return;\r
case LOAD_STORE_FORMAT1_H:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);\r
return;\r
case LOAD_STORE_FORMAT1_B:\r
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);\r
return;\r
\r
case LOAD_STORE_FORMAT2:\r
// A6.5.1 <Rd>, [<Rn>, <Rm>]\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);\r
return;\r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);\r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);\r
return;\r
- \r
+\r
case LOAD_STORE_MULTIPLE_FORMAT1:\r
// <Rn>!, {r0-r7}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));\r
return;\r
- \r
+\r
case POP_FORMAT:\r
// POP {r0-r7,pc}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0))); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));\r
return;\r
\r
case PUSH_FORMAT:\r
// PUSH {r0-r7,lr}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0))); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));\r
return;\r
\r
- \r
+\r
case IMMED_8:\r
// A6.7 <immed_8>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);\r
return;\r
\r
case CONDITIONAL_BRANCH:\r
Cond = gCondition[(OpCode >> 8) & 0xf];\r
Buf[Offset-5] = *Cond++;\r
Buf[Offset-4] = *Cond;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
return;\r
case UNCONDITIONAL_BRANCH_SHORT:\r
// A6.3.2 B <target_address>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11)); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
return;\r
- \r
+\r
case BRANCH_EXCHANGE:\r
// A6.3.3 BX|BLX <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);\r
return;\r
\r
case DATA_FORMAT1:\r
// A6.4.3 <Rd>, <Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);\r
return;\r
case DATA_FORMAT2:\r
// A6.4.3 <Rd>, <Rn>, #3_bit_immed\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);\r
return;\r
case DATA_FORMAT3:\r
// A6.4.3 <Rd>|<Rn>, #imm8\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);\r
return;\r
case DATA_FORMAT4:\r
// A6.4.3 <Rd>|<Rm>, #immed_5\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);\r
return;\r
case DATA_FORMAT5:\r
// A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);\r
return;\r
case DATA_FORMAT6_SP:\r
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
return;\r
case DATA_FORMAT6_PC:\r
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);\r
return;\r
case DATA_FORMAT7:\r
// A6.4.3 SP, SP, #<7_Bit_immed>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);\r
return;\r
case DATA_FORMAT8:\r
// A6.4.3 <Rd>|<Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);\r
return;\r
- \r
+\r
case CPS_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f"); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
return;\r
\r
case ENDIAN_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE"); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");\r
return;\r
\r
case DATA_CBZ:\r
// CB{N}Z <Rn>, <Lable>\r
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);\r
return;\r
\r
case ADR_FORMAT:\r
// ADR <Rd>, <Label>\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);\r
return;\r
\r
case IT_BLOCK:\r
// ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]\r
// ITSTATE[7:5] == cond[3:1]\r
- // ITSTATE[4] == 1st Instruction cond[0] \r
- // ITSTATE[3] == 2st Instruction cond[0] \r
- // ITSTATE[2] == 3st Instruction cond[0] \r
+ // ITSTATE[4] == 1st Instruction cond[0]\r
+ // ITSTATE[3] == 2st Instruction cond[0]\r
+ // ITSTATE[2] == 3st Instruction cond[0]\r
// ITSTATE[1] == 4st Instruction cond[0]\r
// ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions\r
// 1st one in ITSTATE low bits defines the number of instructions\r
} else if ((OpCode & 0xf) == 0x8) {\r
*ItBlock = 1;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);\r
return;\r
}\r
}\r
}\r
\r
- \r
+\r
// Thumb2 are 32-bit instructions\r
*OpCodePtrPtr += 1;\r
Rt = (OpCode32 >> 12) & 0xf;\r
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {\r
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {\r
if (Extended) {\r
- Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);\r
} else {\r
- Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start); \r
+ Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);\r
}\r
switch (gOpThumb2[Index].AddressMode) {\r
case B_T3:\r
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1\r
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S\r
Target = SignExtend32 (Target, BIT20);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
return;\r
case B_T4:\r
// S:I1:I2:imm10:imm11:0\r
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1\r
Target |= (S ? BIT24 : 0); // S\r
Target = SignExtend32 (Target, BIT24);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
return;\r
\r
case BL_T2:\r
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1\r
Target |= (S ? BIT25 : 0); // S\r
Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);\r
return;\r
\r
case POP_T2:\r
return;\r
\r
case POP_T3:\r
- // <register> \r
+ // <register>\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);\r
return;\r
\r
\r
case LDM_REG_IMM12_SIGNED:\r
// <rt>, <label>\r
- Target = OpCode32 & 0xfff; \r
+ Target = OpCode32 & 0xfff;\r
if ((OpCode32 & BIT23) == 0) {\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);\r
}\r
return;\r
- \r
+\r
case LDM_REG_IMM12:\r
// <rt>, [<rn>, {, #<imm12>]}\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
case LDRD_REG_IMM8_SIGNED:\r
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
P = (OpCode32 & BIT24) == BIT24; // index = P\r
- U = (OpCode32 & BIT23) == BIT23; \r
+ U = (OpCode32 & BIT23) == BIT23;\r
W = (OpCode32 & BIT21) == BIT21;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
if (P) {\r
}\r
return;\r
\r
- case LDRD_REG_IMM8: \r
- // LDRD <rt>, <rt2>, <label> \r
- Target = (OpCode32 & 0xff) << 2; \r
+ case LDRD_REG_IMM8:\r
+ // LDRD <rt>, <rt2>, <label>\r
+ Target = (OpCode32 & 0xff) << 2;\r
if ((OpCode32 & BIT23) == 0) {\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
// LDREXD <Rt>, <Rt2>, [<Rn>]\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
return;\r
- \r
+\r
case SRS_FORMAT:\r
// SP{!}, #<mode>\r
W = (OpCode32 & BIT21) == BIT21;\r
W = (OpCode32 & BIT21) == BIT21;\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
return;\r
- \r
+\r
case ADD_IMM12:\r
// ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8\r
if ((OpCode32 & BIT20) == BIT20) {\r
Buf[Offset - 3] = 'S'; // assume %-6a\r
}\r
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);\r
return;\r
\r
case ADD_IMM12_1REG:\r
Buf[Offset - 3] = 'S'; // assume %-6a\r
}\r
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
return;\r
\r
case THUMB2_IMM16:\r
// MOVW <Rd>, #<const> i:imm3:imm8\r
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
Target |= ((OpCode32 >> 4) & 0xf0000);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);\r
return;\r
\r
case ADD_IMM5:\r
Buf[Offset - 3] = 'S'; // assume %-6a\r
}\r
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]); \r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
if (Target != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
}\r
return;\r
\r
case ADD_IMM5_2REG:\r
// CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]); \r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);\r
if (Target != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);\r
}\r
\r
\r
Buf[Offset - 3] = 'S'; // assume %-6a\r
}\r
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);\r
return;\r
\r
case ASR_3REG:\r
if ((OpCode32 & BIT20) == BIT20) {\r
Buf[Offset - 3] = 'S'; // assume %-6a\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);\r
return;\r
\r
case ADR_THUMB2:\r
} else {\r
Target = PCAlign4 (PC) + Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);\r
return;\r
\r
case CMN_THUMB2:\r
// CMN <Rn>, #<const>}\r
Target = (OpCode32 & 0xff) | ((OpCode >> 4) && 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);\r
return;\r
\r
case BFC_THUMB2:\r
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){\r
// BFC <Rd>, #<lsb>, #<width>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);\r
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1); \r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);\r
}\r
return;\r
\r
if (opc2 != 0) {\r
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
}\r
- return; \r
+ return;\r
\r
case MRRC_THUMB2:\r
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);\r
- return; \r
+ return;\r
\r
case THUMB2_2REGS:\r
// <Rd>, <Rm>\r
// MRS <Rd>, CPSR\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);\r
return;\r
- \r
+\r
case THUMB2_MSR:\r
// MRS CPSR_<fields>, <Rd>\r
Target = (OpCode32 >> 10) & 3;\r
\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to \r
- point to next instructin. \r
- \r
- We cheat and only decode instructions that access \r
+ Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instructin.\r
+\r
+ We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
- \r
- @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble. \r
+\r
+ @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.\r
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream\r
@param Extended TRUE dump hex for instruction too.\r
@param ItBlock Size of IT Block\r
@param Buf Buffer to sprintf disassembly into.\r
- @param Size Size of Buf in bytes. \r
- \r
+ @param Size Size of Buf in bytes.\r
+\r
**/\r
VOID\r
DisassembleInstruction (\r
DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);\r
}\r
}\r
- \r
+\r
projects / mirror_edk2.git / blobdiff