ArmPkg BeagleBoardPkg Omap35xxPkg: fix typo 'ArmDataSyncronizationBarrier'

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Support.S

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 66c310bb3194820a704c0466b6c500f8757b165a..8b5e0fb6e7fe7d86ebcb9834e2bae4da24adc194 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -42,15 +42,13 @@ GCC_ASM_EXPORT (ArmDisableBranchPrediction)
 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
 GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)\r
 GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
+GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
 GCC_ASM_EXPORT (ArmWriteVBar)\r
-GCC_ASM_EXPORT (ArmVFPImplemented)\r
+GCC_ASM_EXPORT (ArmReadVBar)\r
 GCC_ASM_EXPORT (ArmEnableVFP)\r
 GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
 GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
 GCC_ASM_EXPORT (ArmReadTpidrurw)\r
 GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
@@ -125,18 +123,20 @@ ASM_PFX(ArmEnableMmu):
 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: tlbi    vmalle1\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el1, x0       // Write back\r
    b       4f\r
 2: tlbi    alle2\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el2, x0       // Write back\r
    b       4f\r
 3: tlbi    alle3\r
+   dsb     nsh\r
    isb\r
    msr     sctlr_el3, x0       // Write back\r
-4: dsb     sy\r
-   isb\r
+4: isb\r
    ret\r
 \r
 \r
@@ -147,7 +147,7 @@ ASM_PFX(ArmDisableMmu):
 2: mrs     x0, sctlr_el2        // Read System Control Register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Read System Control Register EL3\r
-4: bic     x0, x0, #CTRL_M_BIT  // Clear MMU enable bit\r
+4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back\r
    tlbi    vmalle1\r
@@ -169,9 +169,8 @@ ASM_PFX(ArmDisableCachesAndMmu):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_M_BIT  // Disable MMU\r
-   bic     x0, x0, #CTRL_C_BIT  // Disable D Cache\r
-   bic     x0, x0, #CTRL_I_BIT  // Disable I Cache\r
+4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches\r
+   and     x0, x0, x1\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -220,7 +219,7 @@ ASM_PFX(ArmDisableDataCache):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_C_BIT  // Clear C bit\r
+4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -258,7 +257,7 @@ ASM_PFX(ArmDisableInstructionCache):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_I_BIT  // Clear I bit\r
+4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -292,7 +291,7 @@ ASM_PFX(ArmDisableAlignmentCheck):
 2: mrs     x0, sctlr_el2        // Get control register EL2\r
    b       4f\r
 3: mrs     x0, sctlr_el3        // Get control register EL3\r
-4: bic     x0, x0, #CTRL_A_BIT  // Clear A (alignment check) bit\r
+4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit\r
    EL1_OR_EL2_OR_EL3(x1)\r
 1: msr     sctlr_el1, x0        // Write back control register\r
    b       4f\r
@@ -316,8 +315,8 @@ ASM_PFX(ArmDisableBranchPrediction):
 \r
 ASM_PFX(AArch64AllDataCachesOperation):\r
 // We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+  str   x30, [sp, #-16]!\r
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
@@ -329,8 +328,8 @@ ASM_PFX(AArch64AllDataCachesOperation):
 \r
 ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
 // We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+  str   x30, [sp, #-16]!\r
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)\r
@@ -390,7 +389,7 @@ ASM_PFX(ArmDataMemoryBarrier):
   ret\r
 \r
 \r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
+ASM_PFX(ArmDataSynchronizationBarrier):\r
 ASM_PFX(ArmDrainWriteBuffer):\r
   dsb   sy\r
   ret\r
@@ -411,6 +410,16 @@ ASM_PFX(ArmWriteVBar):
 4: isb\r
    ret\r
 \r
+ASM_PFX(ArmReadVBar):\r
+   EL1_OR_EL2_OR_EL3(x1)\r
+1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register\r
+   ret\r
+2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register\r
+   ret\r
+3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register\r
+   ret\r
+\r
+\r
 ASM_PFX(ArmEnableVFP):\r
   // Check whether floating-point is implemented in the processor.\r
   mov   x1, x30                 // Save LR\r
@@ -442,25 +451,10 @@ ASM_PFX(ArmCallWFI):
   ret\r
 \r
 \r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
-   EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  vmalle1\r
-   b     4f\r
-2: tlbi  alle2\r
-   b     4f\r
-3: tlbi  alle3\r
-4: dsb   sy\r
-   isb\r
-   ret\r
-\r
-\r
 ASM_PFX(ArmReadMpidr):\r
   mrs   x0, mpidr_el1           // read EL1 MPIDR\r
   ret\r
 \r
-ASM_PFX(ArmReadMidr):\r
-  mrs   x0, midr_el1            // Read Main ID Register\r
-  ret\r
 \r
 // Keep old function names for C compatibilty for now. Change later?\r
 ASM_PFX(ArmReadTpidrurw):\r