Replace all instances of ArmDataSyncronizationBarrier with
ArmDataSynchronizationBarrier.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18751
6f19259b-4bc3-4df7-8a09-
765794883524
\r
VOID\r
EFIAPI\r
-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r
VOID\r
);\r
\r
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)\r
GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
+GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmWriteVBar)\r
GCC_ASM_EXPORT (ArmReadVBar)\r
ret\r
\r
\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
+ASM_PFX(ArmDataSynchronizationBarrier):\r
ASM_PFX(ArmDrainWriteBuffer):\r
dsb sy\r
ret\r
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r
GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)\r
GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
+GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmReadVBar)\r
GCC_ASM_EXPORT (ArmWriteVBar)\r
dmb\r
bx LR\r
\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
+ASM_PFX(ArmDataSynchronizationBarrier):\r
ASM_PFX(ArmDrainWriteBuffer):\r
dsb\r
bx LR\r
EXPORT ArmV7AllDataCachesOperation\r
EXPORT ArmV7PerformPoUDataCacheOperation\r
EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSyncronizationBarrier\r
+ EXPORT ArmDataSynchronizationBarrier\r
EXPORT ArmInstructionSynchronizationBarrier\r
EXPORT ArmReadVBar\r
EXPORT ArmWriteVBar\r
dmb\r
bx LR\r
\r
-ArmDataSyncronizationBarrier\r
+ArmDataSynchronizationBarrier\r
ArmDrainWriteBuffer\r
dsb\r
bx LR\r
\r
// Turn off the functional clock for Timer 3\r
MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
\r
// Clear IRQs\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
\r
return RETURN_SUCCESS;\r
}\r
)\r
{\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
return EFI_SUCCESS;\r
}\r
\r
\r
// Needed to prevent infinite nesting when Time Driver lowers TPL\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
\r
InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
if (InterruptHandler != NULL) {\r
\r
// Needed to clear after running the handler\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
}\r
\r
//\r
while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);\r
\r
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);\r
- ArmDataSyncronizationBarrier ();\r
+ ArmDataSynchronizationBarrier ();\r
\r
}\r
\r