+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmCleanDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmEnableMmu)\r
-GCC_ASM_EXPORT(ArmDisableMmu)\r
-GCC_ASM_EXPORT(ArmMmuEnabled)\r
-GCC_ASM_EXPORT(ArmEnableDataCache)\r
-GCC_ASM_EXPORT(ArmDisableDataCache)\r
-GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
-GCC_ASM_EXPORT(ArmSetLowVectors)\r
-GCC_ASM_EXPORT(ArmSetHighVectors)\r
-GCC_ASM_EXPORT(ArmIsMpCore)\r
-GCC_ASM_EXPORT(ArmCallWFI)\r
-GCC_ASM_EXPORT(ArmReadMpidr)\r
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT(ArmEnableFiq)\r
-GCC_ASM_EXPORT(ArmDisableFiq)\r
-GCC_ASM_EXPORT(ArmEnableInterrupts)\r
-GCC_ASM_EXPORT(ArmDisableInterrupts)\r
-GCC_ASM_EXPORT (ArmEnableVFP)\r
-\r
-Arm11PartNumberMask: .word 0xFFF0\r
-Arm11PartNumber: .word 0xB020\r
-\r
-.set DC_ON, (0x1<<2)\r
-.set IC_ON, (0x1<<12)\r
-.set XP_ON, (0x1<<23)\r
-.set CTRL_M_BIT, (1 << 0)\r
-.set CTRL_C_BIT, (1 << 2)\r
-.set CTRL_I_BIT, (1 << 12)\r
-\r
-ASM_PFX(ArmDisableCachesAndMmu):\r
- mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
- bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
- bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
- bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
- mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
- bx LR\r
-\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanDataCache):\r
- mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCache):\r
- mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmInvalidateDataCache):\r
- mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
- mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
- bx lr\r
-\r
-ASM_PFX(ArmEnableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- bx LR\r
-\r
-ASM_PFX(ArmMmuEnabled):\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Data synchronization barrier\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableDataCache):\r
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableDataCache):\r
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableInstructionCache):\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set I bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableInstructionCache):\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear I bit.\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableBranchPrediction):\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableBranchPrediction):\r
- mrc p15, 0, r0, c1, c0, 0\r
- bic r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #5\r
- bx LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #4\r
- bx LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C5, #4\r
- bx LR\r
-\r
-ASM_PFX(ArmSetLowVectors):\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- bx LR\r
-\r
-ASM_PFX(ArmSetHighVectors):\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- bx LR\r
-\r
-ASM_PFX(ArmIsMpCore):\r
- push { r1 }\r
- mrc p15, 0, r0, c0, c0, 0\r
- # Extract Part Number to check it is an ARM11MP core (0xB02)\r
- LoadConstantToReg (Arm11PartNumberMask, r1)\r
- and r0, r0, r1\r
- LoadConstantToReg (Arm11PartNumber, r1)\r
- cmp r0, r1\r
- movne r0, #0\r
- pop { r1 }\r
- bx lr\r
-\r
-ASM_PFX(ArmCallWFI):\r
- wfi\r
- bx lr\r
-\r
-ASM_PFX(ArmReadMpidr):\r
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
- bx lr\r
-\r
-ASM_PFX(ArmEnableFiq):\r
- mrs R0,CPSR\r
- bic R0,R0,#0x40 @Enable FIQ interrupts\r
- msr CPSR_c,R0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableFiq):\r
- mrs R0,CPSR\r
- orr R1,R0,#0x40 @Disable FIQ interrupts\r
- msr CPSR_c,R1\r
- tst R0,#0x80\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableInterrupts):\r
- mrs R0,CPSR\r
- bic R0,R0,#0x80 @Enable IRQ interrupts\r
- msr CPSR_c,R0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableInterrupts):\r
- mrs R0,CPSR\r
- orr R1,R0,#0x80 @Disable IRQ interrupts\r
- msr CPSR_c,R1\r
- tst R0,#0x80\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableVFP):\r
- # Read CPACR (Coprocessor Access Control Register)\r
- mrc p15, 0, r0, c1, c0, 2\r
- # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
- orr r0, r0, #0x00f00000\r
- # Write back CPACR (Coprocessor Access Control Register)\r
- mcr p15, 0, r0, c1, c0, 2\r
- # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
- mov r0, #0x40000000\r
- #TODO: Fixme - need compilation flag\r
- #fmxr FPEXC, r0\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
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